^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PROG_ID_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PROG_STATUS_MASK(id) (1 << ((id) + 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PROG_MAX_RM9200_CSS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_programmable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const struct clk_programmable_layout *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_programmable *prog = to_clk_programmable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct clk_programmable_layout *layout = prog->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int pckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (layout->is_pres_direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) rate = parent_rate / (PROG_PRES(layout, pckr) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rate = parent_rate >> PROG_PRES(layout, pckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int clk_programmable_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_programmable *prog = to_clk_programmable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct clk_programmable_layout *layout = prog->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) long best_rate = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long tmp_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) parent = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (layout->is_pres_direct) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (shift = 0; shift <= layout->pres_mask; shift++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tmp_rate = parent_rate / (shift + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (tmp_rate <= req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for (shift = 0; shift < layout->pres_mask; shift++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tmp_rate = parent_rate >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (tmp_rate <= req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (tmp_rate > req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (best_rate < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (req->rate - tmp_rate) < (req->rate - best_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) req->best_parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!best_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (best_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk_programmable *prog = to_clk_programmable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct clk_programmable_layout *layout = prog->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int mask = layout->css_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int pckr = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (layout->have_slck_mck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mask |= AT91_PMC_CSSMCK_MCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (prog->mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pckr = clk_mux_index_to_val(prog->mux_table, 0, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (index > layout->css_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pckr |= AT91_PMC_CSSMCK_MCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), mask, pckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static u8 clk_programmable_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_programmable *prog = to_clk_programmable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct clk_programmable_layout *layout = prog->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int pckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = pckr & layout->css_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (layout->have_slck_mck && (pckr & AT91_PMC_CSSMCK_MCK) && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = PROG_MAX_RM9200_CSS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (prog->mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = clk_mux_val_to_index(&prog->hw, prog->mux_table, 0, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk_programmable *prog = to_clk_programmable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct clk_programmable_layout *layout = prog->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (layout->is_pres_direct) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) shift = div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (shift > layout->pres_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) shift = fls(div) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (div != (1 << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (shift >= layout->pres_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) layout->pres_mask << layout->pres_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) shift << layout->pres_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct clk_ops programmable_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .recalc_rate = clk_programmable_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .determine_rate = clk_programmable_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .get_parent = clk_programmable_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .set_parent = clk_programmable_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .set_rate = clk_programmable_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) at91_clk_register_programmable(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const char *name, const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 num_parents, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct clk_programmable_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 *mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct clk_programmable *prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (id > PROG_ID_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) prog = kzalloc(sizeof(*prog), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!prog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) init.ops = &programmable_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) prog->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) prog->layout = layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) prog->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) prog->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) prog->mux_table = mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hw = &prog->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = clk_hw_register(NULL, &prog->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) kfree(prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pmc_register_pck(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct clk_programmable_layout at91rm9200_programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .pres_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pres_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .css_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .have_slck_mck = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .is_pres_direct = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct clk_programmable_layout at91sam9g45_programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .pres_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .pres_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .css_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .have_slck_mck = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .is_pres_direct = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct clk_programmable_layout at91sam9x5_programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pres_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .pres_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .css_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .have_slck_mck = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .is_pres_direct = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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