^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk_plldiv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_plldiv *plldiv = to_clk_plldiv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int mckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (mckr & AT91_PMC_PLLADIV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (rate > *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) div = *parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (rate < div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (rate - div < *parent_rate - rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_plldiv *plldiv = to_clk_plldiv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if ((parent_rate != rate) && (parent_rate / 2 != rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) parent_rate != rate ? AT91_PMC_PLLADIV2 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct clk_ops plldiv_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .recalc_rate = clk_plldiv_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .round_rate = clk_plldiv_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .set_rate = clk_plldiv_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) at91_clk_register_plldiv(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_plldiv *plldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!plldiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) init.ops = &plldiv_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) plldiv->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) plldiv->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) hw = &plldiv->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = clk_hw_register(NULL, &plldiv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) kfree(plldiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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