^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_DIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_DIV_MAX PLL_DIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) (layout)->mul_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_MUL_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_ICPR_SHIFT(id) ((id) * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_MAX_COUNT 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_COUNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_OUT_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_MAX_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct clk_pll_layout *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct clk_pll_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline bool clk_pll_ready(struct regmap *regmap, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_read(regmap, AT91_PMC_SR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return status & PLL_STATUS_MASK(id) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int clk_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct regmap *regmap = pll->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct clk_pll_layout *layout = pll->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const struct clk_pll_characteristics *characteristics =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pll->characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 id = pll->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 mask = PLL_STATUS_MASK(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int offset = PLL_REG(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int pllr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regmap_read(regmap, offset, &pllr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) div = PLL_DIV(pllr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mul = PLL_MUL(pllr, layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regmap_read(regmap, AT91_PMC_SR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if ((status & mask) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (div == pll->div && mul == pll->mul))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (characteristics->out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) out = characteristics->out[pll->range];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (characteristics->icpll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_update_bits(regmap, offset, layout->pllr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (out << PLL_OUT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ((pll->mul & layout->mul_mask) << layout->mul_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) while (!clk_pll_ready(regmap, pll->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int clk_pll_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return clk_pll_ready(pll->regmap, pll->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void clk_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int mask = pll->layout->pllr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!pll->div || !pll->mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return (parent_rate / pll->div) * (pll->mul + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 *div, u32 *mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 *index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct clk_pll_layout *layout = pll->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct clk_pll_characteristics *characteristics =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pll->characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long bestremainder = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long maxdiv, mindiv, tmpdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) long bestrate = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long bestdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long bestmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Check if parent_rate is a valid input rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (parent_rate < characteristics->input.min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Calculate minimum divider based on the minimum multiplier, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * parent_rate and the requested rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Should always be 2 according to the input and output characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * of the PLL blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mindiv = (parent_rate * PLL_MUL_MIN) / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!mindiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mindiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (parent_rate > characteristics->input.max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (tmpdiv > PLL_DIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (tmpdiv > mindiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mindiv = tmpdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Calculate the maximum divider which is limited by PLL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * layout (limited by the MUL or DIV field size).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (maxdiv > PLL_DIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) maxdiv = PLL_DIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Iterate over the acceptable divider values to find the best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * divider/multiplier pair (the one that generates the closest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * rate to the requested one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long tmpmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Calculate the multiplier associated with the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * divider that provide the closest rate to the requested one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tmprate = (parent_rate / tmpdiv) * tmpmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (tmprate > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) remainder = tmprate - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) remainder = rate - tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Compare the remainder with the best remainder found until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * now and elect a new best multiplier/divider pair if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * current remainder is smaller than the best one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (remainder < bestremainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bestremainder = remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bestdiv = tmpdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bestmul = tmpmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bestrate = tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * We've found a perfect match!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Stop searching now and use this multiplier/divider pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!remainder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* We haven't found any multiplier/divider pair => return -ERANGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (bestrate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return bestrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Check if bestrate is a valid output rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < characteristics->num_output; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (bestrate >= characteristics->output[i].min &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bestrate <= characteristics->output[i].max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (i >= characteristics->num_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *div = bestdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *mul = bestmul - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return bestrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) &div, &mul, &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pll->range = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pll->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pll->mul = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct clk_ops pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .unprepare = clk_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .is_prepared = clk_pll_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) at91_clk_register_pll(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const char *parent_name, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const struct clk_pll_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct clk_pll_characteristics *characteristics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int offset = PLL_REG(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int pllr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (id > PLL_MAX_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) init.ops = &pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pll->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pll->layout = layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pll->characteristics = characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pll->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_read(regmap, offset, &pllr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pll->div = PLL_DIV(pllr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pll->mul = PLL_MUL(pllr, layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = clk_hw_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const struct clk_pll_layout at91rm9200_pll_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .pllr_mask = 0x7FFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .mul_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .mul_mask = 0x7FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const struct clk_pll_layout at91sam9g45_pll_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .pllr_mask = 0xFFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .mul_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .mul_mask = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const struct clk_pll_layout at91sam9g20_pllb_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .pllr_mask = 0x3FFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .mul_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .mul_mask = 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const struct clk_pll_layout sama5d3_pll_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .pllr_mask = 0x1FFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .mul_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .mul_mask = 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags