Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright (C) 2018 Microchip Technology Inc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *                     Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <soc/at91/atmel-sfr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_i2s_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u8 bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define to_clk_i2s_mux(hw) container_of(hw, struct clk_i2s_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static u8 clk_i2s_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return (val & BIT(mux->bus_id)) >> mux->bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				  BIT(mux->bus_id), index << mux->bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct clk_ops clk_i2s_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.get_parent = clk_i2s_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.set_parent = clk_i2s_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			  const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			  unsigned int num_parents, u8 bus_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct clk_i2s_mux *i2s_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (!i2s_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	init.ops = &clk_i2s_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	i2s_ck->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	i2s_ck->bus_id = bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	i2s_ck->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	ret = clk_hw_register(NULL, &i2s_ck->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		kfree(i2s_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	return &i2s_ck->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }