^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clk-h32mx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Alexandre Belloni <alexandre.belloni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define H32MX_MAX_FREQ 90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_sama5d4_h32mx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int mckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (mckr & AT91_PMC_H32MXDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (parent_rate > H32MX_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pr_warn("H32MX clock is too fast\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (rate > *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) div = *parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (rate < div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (rate - div < *parent_rate - rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 mckr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (parent_rate != rate && (parent_rate / 2) != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if ((parent_rate / 2) == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mckr = AT91_PMC_H32MXDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AT91_PMC_H32MXDIV, mckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const struct clk_ops h32mx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .round_rate = clk_sama5d4_h32mx_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .set_rate = clk_sama5d4_h32mx_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) at91_clk_register_h32mx(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk_sama5d4_h32mx *h32mxclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!h32mxclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) init.ops = &h32mx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) h32mxclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) h32mxclk->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = clk_hw_register(NULL, &h32mxclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) kfree(h32mxclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return &h32mxclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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