^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const struct clk_master_characteristics sam9rl_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) .output = { .min = 0, .max = 94000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .divisors = { 1, 2, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static u8 sam9rl_plla_out[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct clk_range sam9rl_plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { .min = 80000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { .min = 190000000, .max = 240000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct clk_pll_characteristics sam9rl_plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .input = { .min = 1000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .num_output = ARRAY_SIZE(sam9rl_plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .output = sam9rl_plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .out = sam9rl_plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } at91sam9rl_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } at91sam9rl_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .n = "pioA_clk", .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .n = "pioB_clk", .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .n = "pioC_clk", .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .n = "pioD_clk", .id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .n = "usart0_clk", .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .n = "usart1_clk", .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .n = "usart2_clk", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .n = "usart3_clk", .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .n = "mci0_clk", .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .n = "twi0_clk", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .n = "twi1_clk", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .n = "spi0_clk", .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .n = "ssc0_clk", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .n = "ssc1_clk", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .n = "tc0_clk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .n = "tc1_clk", .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .n = "tc2_clk", .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .n = "pwm_clk", .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .n = "adc_clk", .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .n = "dma0_clk", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .n = "udphs_clk", .id = 22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .n = "lcd_clk", .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void __init at91sam9rl_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const char *slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct pmc_data *at91sam9rl_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) i = of_property_match_string(np, "clock-names", "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) nck(at91sam9rl_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) nck(at91sam9rl_periphck), 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!at91sam9rl_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) at91sam9rl_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &sam9rl_plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) at91sam9rl_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &at91rm9200_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &sam9rl_mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) at91sam9rl_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) parent_names, 5, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &at91rm9200_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) at91sam9rl_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) at91sam9rl_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) at91sam9rl_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) hw = at91_clk_register_peripheral(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) at91sam9rl_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) at91sam9rl_periphck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) kfree(at91sam9rl_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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