Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static const struct clk_master_characteristics mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	.output = { .min = 0, .max = 133333333 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	.divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	.have_div3_pres = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static const struct clk_range plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	{ .min = 745000000, .max = 800000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	{ .min = 695000000, .max = 750000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{ .min = 645000000, .max = 700000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{ .min = 595000000, .max = 650000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{ .min = 545000000, .max = 600000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{ .min = 495000000, .max = 555000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{ .min = 445000000, .max = 500000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{ .min = 400000000, .max = 450000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct clk_pll_characteristics plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.input = { .min = 2000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.num_output = ARRAY_SIZE(plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.output = plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.icpll = plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.out = plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static u8 pllb_out[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static const struct clk_range pllb_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ .min = 30000000, .max = 100000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const struct clk_pll_characteristics pllb_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.input = { .min = 2000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.num_output = ARRAY_SIZE(pllb_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.output = pllb_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.out = pllb_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) } at91sam9n12_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ .n = "ddrck", .p = "masterck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ .n = "lcdck", .p = "masterck", .id = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ .n = "uhpck", .p = "usbck",    .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ .n = "udpck", .p = "usbck",    .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ .n = "pck0",  .p = "prog0",    .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .n = "pck1",  .p = "prog1",    .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.offset = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.cmd = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.pid_mask = GENMASK(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.div_mask = GENMASK(17, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct pck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const struct pck at91sam9n12_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ .n = "pioAB_clk",  .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ .n = "pioCD_clk",  .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ .n = "fuse_clk",   .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ .n = "usart0_clk", .id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ .n = "usart1_clk", .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ .n = "usart2_clk", .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ .n = "usart3_clk", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ .n = "twi0_clk",   .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ .n = "twi1_clk",   .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ .n = "mci0_clk",   .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ .n = "spi0_clk",   .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ .n = "spi1_clk",   .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ .n = "uart0_clk",  .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ .n = "uart1_clk",  .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ .n = "tcb_clk",    .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ .n = "pwm_clk",    .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ .n = "adc_clk",    .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ .n = "dma0_clk",   .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{ .n = "uhphs_clk",  .id = 22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ .n = "udphs_clk",  .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ .n = "lcdc_clk",   .id = 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ .n = "sha_clk",    .id = 27, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{ .n = "ssc0_clk",   .id = 28, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{ .n = "aes_clk",    .id = 29, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ .n = "trng_clk",   .id = 30, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __init at91sam9n12_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const char *slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct pmc_data *at91sam9n12_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	i = of_property_match_string(np, "clock-names", "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 					   nck(at91sam9n12_systemck), 31, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (!at91sam9n12_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					   50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	parent_names[0] = "main_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	parent_names[1] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	at91sam9n12_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				   &at91rm9200_pll_layout, &plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				   &at91rm9200_pll_layout, &pllb_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				      &at91sam9x5_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				      &mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	at91sam9n12_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 						    parent_names, 5, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 						    &at91sam9x5_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 						    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		at91sam9n12_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					      at91sam9n12_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					      at91sam9n12_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 							 &at91sam9n12_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 							 at91sam9n12_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 							 "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 							 at91sam9n12_periphck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 							 &range, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	kfree(at91sam9n12_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * The TCB is used as the clocksource so its clock is needed early. This means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * this can't be a platform driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		      at91sam9n12_pmc_setup);