^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const struct clk_master_characteristics mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) .output = { .min = 0, .max = 133333333 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const struct clk_range plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { .min = 745000000, .max = 800000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { .min = 695000000, .max = 750000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { .min = 645000000, .max = 700000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { .min = 595000000, .max = 650000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { .min = 545000000, .max = 600000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { .min = 495000000, .max = 555000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { .min = 445000000, .max = 500000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { .min = 400000000, .max = 450000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct clk_pll_characteristics plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .input = { .min = 2000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .num_output = ARRAY_SIZE(plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .output = plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .icpll = plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .out = plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } at91sam9g45_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .n = "ddrck", .p = "masterck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .n = "uhpck", .p = "usbck", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct pck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct pck at91sam9g45_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .n = "pioA_clk", .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .n = "pioB_clk", .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .n = "pioC_clk", .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .n = "pioDE_clk", .id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .n = "trng_clk", .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .n = "usart0_clk", .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .n = "usart1_clk", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .n = "usart2_clk", .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .n = "usart3_clk", .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .n = "mci0_clk", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .n = "twi0_clk", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .n = "twi1_clk", .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .n = "spi0_clk", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .n = "spi1_clk", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .n = "ssc0_clk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .n = "ssc1_clk", .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .n = "tcb0_clk", .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .n = "pwm_clk", .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .n = "adc_clk", .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .n = "dma0_clk", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .n = "uhphs_clk", .id = 22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .n = "lcd_clk", .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .n = "ac97_clk", .id = 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .n = "macb0_clk", .id = 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .n = "isi_clk", .id = 26, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .n = "udphs_clk", .id = 27, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .n = "aestdessha_clk", .id = 28, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .n = "mci1_clk", .id = 29, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .n = "vdec_clk", .id = 30, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init at91sam9g45_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pmc_data *at91sam9g45_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) i = of_property_match_string(np, "clock-names", "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) nck(at91sam9g45_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) nck(at91sam9g45_periphck), 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!at91sam9g45_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) at91sam9g45_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &at91rm9200_pll_layout, &plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) at91sam9g45_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &at91rm9200_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) &mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) at91sam9g45_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) parent_names[0] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) parent_names[1] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) parent_names, 5, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &at91sam9g45_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) at91sam9g45_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) at91sam9g45_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) at91sam9g45_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) hw = at91_clk_register_peripheral(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) at91sam9g45_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) at91sam9g45_periphck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) kfree(at91sam9g45_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * The TCB is used as the clocksource so its clock is needed early. This means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * this can't be a platform driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) at91sam9g45_pmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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