^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct sck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct pck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct at91sam926x_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct clk_pll_layout *plla_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) const struct clk_pll_characteristics *plla_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct clk_pll_layout *pllb_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) const struct clk_pll_characteristics *pllb_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const struct clk_master_characteristics *mck_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct sck *sck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct pck *pck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 num_sck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 num_pck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 num_progck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool has_slck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct clk_master_characteristics sam9260_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .output = { .min = 0, .max = 105000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .divisors = { 1, 2, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static u8 sam9260_plla_out[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static u16 sam9260_plla_icpll[] = { 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct clk_range sam9260_plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .min = 80000000, .max = 160000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .min = 150000000, .max = 240000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct clk_pll_characteristics sam9260_plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .input = { .min = 1000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .num_output = ARRAY_SIZE(sam9260_plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .output = sam9260_plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .icpll = sam9260_plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .out = sam9260_plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static u8 sam9260_pllb_out[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u16 sam9260_pllb_icpll[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct clk_range sam9260_pllb_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .min = 70000000, .max = 130000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct clk_pll_characteristics sam9260_pllb_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .input = { .min = 1000000, .max = 5000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .num_output = ARRAY_SIZE(sam9260_pllb_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .output = sam9260_pllb_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .icpll = sam9260_pllb_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .out = sam9260_pllb_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct sck at91sam9260_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .n = "uhpck", .p = "usbck", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .n = "udpck", .p = "usbck", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct pck at91sam9260_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .n = "pioA_clk", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .n = "pioB_clk", .id = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .n = "pioC_clk", .id = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .n = "adc_clk", .id = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { .n = "usart0_clk", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .n = "usart1_clk", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .n = "usart2_clk", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .n = "mci0_clk", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .n = "udc_clk", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .n = "twi0_clk", .id = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .n = "spi0_clk", .id = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .n = "spi1_clk", .id = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .n = "ssc0_clk", .id = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .n = "tc0_clk", .id = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .n = "tc1_clk", .id = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .n = "tc2_clk", .id = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .n = "ohci_clk", .id = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .n = "macb0_clk", .id = 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .n = "isi_clk", .id = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .n = "usart3_clk", .id = 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .n = "uart0_clk", .id = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .n = "uart1_clk", .id = 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .n = "tc3_clk", .id = 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .n = "tc4_clk", .id = 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .n = "tc5_clk", .id = 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct at91sam926x_data at91sam9260_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .plla_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .plla_characteristics = &sam9260_plla_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pllb_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .pllb_characteristics = &sam9260_pllb_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mck_characteristics = &sam9260_mck_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .sck = at91sam9260_systemck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_sck = ARRAY_SIZE(at91sam9260_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pck = at91sam9260_periphck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .num_pck = ARRAY_SIZE(at91sam9260_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .num_progck = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .has_slck = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct clk_master_characteristics sam9g20_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .output = { .min = 0, .max = 133000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .divisors = { 1, 2, 4, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct clk_range sam9g20_plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .min = 745000000, .max = 800000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .min = 695000000, .max = 750000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .min = 645000000, .max = 700000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .min = 595000000, .max = 650000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .min = 545000000, .max = 600000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .min = 495000000, .max = 550000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .min = 445000000, .max = 500000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .min = 400000000, .max = 450000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct clk_pll_characteristics sam9g20_plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .input = { .min = 2000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_output = ARRAY_SIZE(sam9g20_plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .output = sam9g20_plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .icpll = sam9g20_plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .out = sam9g20_plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static u8 sam9g20_pllb_out[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u16 sam9g20_pllb_icpll[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct clk_range sam9g20_pllb_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .min = 30000000, .max = 100000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct clk_pll_characteristics sam9g20_pllb_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .input = { .min = 2000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_output = ARRAY_SIZE(sam9g20_pllb_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .output = sam9g20_pllb_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .icpll = sam9g20_pllb_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .out = sam9g20_pllb_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct at91sam926x_data at91sam9g20_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .plla_layout = &at91sam9g45_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .plla_characteristics = &sam9g20_plla_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .pllb_layout = &at91sam9g20_pllb_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pllb_characteristics = &sam9g20_pllb_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .mck_characteristics = &sam9g20_mck_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .sck = at91sam9260_systemck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .num_sck = ARRAY_SIZE(at91sam9260_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pck = at91sam9260_periphck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .num_pck = ARRAY_SIZE(at91sam9260_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .num_progck = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .has_slck = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct clk_master_characteristics sam9261_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .output = { .min = 0, .max = 94000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .divisors = { 1, 2, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct clk_range sam9261_plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .min = 80000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .min = 190000000, .max = 240000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct clk_pll_characteristics sam9261_plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .input = { .min = 1000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .num_output = ARRAY_SIZE(sam9261_plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .output = sam9261_plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .icpll = sam9260_plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .out = sam9260_plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static u8 sam9261_pllb_out[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static u16 sam9261_pllb_icpll[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct clk_range sam9261_pllb_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .min = 70000000, .max = 130000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct clk_pll_characteristics sam9261_pllb_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .input = { .min = 1000000, .max = 5000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .num_output = ARRAY_SIZE(sam9261_pllb_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .output = sam9261_pllb_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .icpll = sam9261_pllb_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .out = sam9261_pllb_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct sck at91sam9261_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .n = "uhpck", .p = "usbck", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .n = "udpck", .p = "usbck", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { .n = "pck2", .p = "prog2", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .n = "pck3", .p = "prog3", .id = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .n = "hclk0", .p = "masterck", .id = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .n = "hclk1", .p = "masterck", .id = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct pck at91sam9261_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { .n = "pioA_clk", .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .n = "pioB_clk", .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .n = "pioC_clk", .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .n = "usart0_clk", .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .n = "usart1_clk", .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .n = "usart2_clk", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .n = "mci0_clk", .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .n = "udc_clk", .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .n = "twi0_clk", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .n = "spi0_clk", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { .n = "spi1_clk", .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .n = "ssc0_clk", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .n = "ssc1_clk", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .n = "ssc2_clk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .n = "tc0_clk", .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .n = "tc1_clk", .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .n = "tc2_clk", .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .n = "ohci_clk", .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .n = "lcd_clk", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct at91sam926x_data at91sam9261_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .plla_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .plla_characteristics = &sam9261_plla_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pllb_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .pllb_characteristics = &sam9261_pllb_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .mck_characteristics = &sam9261_mck_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .sck = at91sam9261_systemck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_sck = ARRAY_SIZE(at91sam9261_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pck = at91sam9261_periphck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .num_pck = ARRAY_SIZE(at91sam9261_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .num_progck = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct clk_master_characteristics sam9263_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .output = { .min = 0, .max = 120000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .divisors = { 1, 2, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct clk_range sam9263_pll_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .min = 80000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .min = 190000000, .max = 240000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct clk_pll_characteristics sam9263_pll_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .input = { .min = 1000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num_output = ARRAY_SIZE(sam9263_pll_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .output = sam9263_pll_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .icpll = sam9260_plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .out = sam9260_plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct sck at91sam9263_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { .n = "uhpck", .p = "usbck", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .n = "udpck", .p = "usbck", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { .n = "pck2", .p = "prog2", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .n = "pck3", .p = "prog3", .id = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct pck at91sam9263_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .n = "pioA_clk", .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .n = "pioB_clk", .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { .n = "pioCDE_clk", .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .n = "usart0_clk", .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .n = "usart1_clk", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .n = "usart2_clk", .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .n = "mci0_clk", .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .n = "mci1_clk", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .n = "can_clk", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .n = "twi0_clk", .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .n = "spi0_clk", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .n = "spi1_clk", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .n = "ssc0_clk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .n = "ssc1_clk", .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { .n = "ac97_clk", .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { .n = "tcb_clk", .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { .n = "pwm_clk", .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { .n = "macb0_clk", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .n = "g2de_clk", .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { .n = "udc_clk", .id = 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { .n = "isi_clk", .id = 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { .n = "lcd_clk", .id = 26, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { .n = "dma_clk", .id = 27, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { .n = "ohci_clk", .id = 29, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct at91sam926x_data at91sam9263_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .plla_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .plla_characteristics = &sam9263_pll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pllb_layout = &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .pllb_characteristics = &sam9263_pll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .mck_characteristics = &sam9263_mck_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .sck = at91sam9263_systemck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .num_sck = ARRAY_SIZE(at91sam9263_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .pck = at91sam9263_periphck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_pck = ARRAY_SIZE(at91sam9263_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_progck = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void __init at91sam926x_pmc_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct at91sam926x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const char *slowxtal_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct pmc_data *at91sam9260_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 usb_div[] = { 1, 2, 4, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const char *slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) i = of_property_match_string(np, "clock-names", "slow_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) slowxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) at91sam9260_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ndck(data->sck, data->num_sck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ndck(data->pck, data->num_pck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0, data->num_progck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!at91sam9260_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) at91sam9260_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (data->has_slck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hw = clk_hw_register_fixed_rate_with_accuracy(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "slow_rc_osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) NULL, 0, 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) parent_names[0] = "slow_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) parent_names[1] = "slow_xtal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw = at91_clk_register_sam9260_slow(regmap, "slck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) at91sam9260_pmc->chws[PMC_SLOW] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) slck_name = "slck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) slck_name = slowxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) data->plla_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) data->plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) at91sam9260_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) data->pllb_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data->pllb_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) at91sam9260_pmc->chws[PMC_PLLBCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &at91rm9200_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) data->mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) at91sam9260_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < data->num_progck; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) parent_names, 4, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &at91rm9200_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) at91sam9260_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) for (i = 0; i < data->num_sck; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hw = at91_clk_register_system(regmap, data->sck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) data->sck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) data->sck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) at91sam9260_pmc->shws[data->sck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; i < data->num_pck; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) hw = at91_clk_register_peripheral(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) data->pck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data->pck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) at91sam9260_pmc->phws[data->pck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) kfree(at91sam9260_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void __init at91sam9260_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) at91sam926x_pmc_setup(np, &at91sam9260_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) at91sam9260_pmc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void __init at91sam9261_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) at91sam926x_pmc_setup(np, &at91sam9261_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) at91sam9261_pmc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void __init at91sam9263_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) at91sam926x_pmc_setup(np, &at91sam9263_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) at91sam9263_pmc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void __init at91sam9g20_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) at91sam926x_pmc_setup(np, &at91sam9g20_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) at91sam9g20_pmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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