^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct sck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct pck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct clk_master_characteristics rm9200_mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .output = { .min = 0, .max = 80000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .divisors = { 1, 2, 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u8 rm9200_pll_out[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct clk_range rm9200_pll_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { .min = 80000000, .max = 160000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .min = 150000000, .max = 180000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct clk_pll_characteristics rm9200_pll_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .input = { .min = 1000000, .max = 32000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .num_output = ARRAY_SIZE(rm9200_pll_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .output = rm9200_pll_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .out = rm9200_pll_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct sck at91rm9200_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .n = "udpck", .p = "usbck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .n = "uhpck", .p = "usbck", .id = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .n = "pck0", .p = "prog0", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .n = "pck1", .p = "prog1", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .n = "pck2", .p = "prog2", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .n = "pck3", .p = "prog3", .id = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct pck at91rm9200_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .n = "pioA_clk", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .n = "pioB_clk", .id = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .n = "pioC_clk", .id = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .n = "pioD_clk", .id = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .n = "usart0_clk", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .n = "usart1_clk", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .n = "usart2_clk", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .n = "usart3_clk", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .n = "mci0_clk", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .n = "udc_clk", .id = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .n = "twi0_clk", .id = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .n = "spi0_clk", .id = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .n = "ssc0_clk", .id = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .n = "ssc1_clk", .id = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .n = "ssc2_clk", .id = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .n = "tc0_clk", .id = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .n = "tc1_clk", .id = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .n = "tc2_clk", .id = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .n = "tc3_clk", .id = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .n = "tc4_clk", .id = 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .n = "tc5_clk", .id = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .n = "ohci_clk", .id = 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .n = "macb0_clk", .id = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void __init at91rm9200_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const char *slowxtal_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pmc_data *at91rm9200_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 usb_div[] = { 1, 2, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) i = of_property_match_string(np, "clock-names", "slow_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) slowxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) nck(at91rm9200_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) nck(at91rm9200_periphck), 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!at91rm9200_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) at91rm9200_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &rm9200_pll_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) at91rm9200_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &at91rm9200_pll_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &rm9200_pll_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) at91rm9200_pmc->chws[PMC_PLLBCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) parent_names[0] = slowxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &at91rm9200_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &rm9200_mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) at91rm9200_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) parent_names[0] = slowxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) parent_names[2] = "pllack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) parent_names[3] = "pllbck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) parent_names, 4, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &at91rm9200_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) at91rm9200_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) at91rm9200_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) at91rm9200_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) hw = at91_clk_register_peripheral(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) at91rm9200_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) at91rm9200_periphck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) kfree(at91rm9200_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * While the TCB can be used as the clocksource, the system timer is most likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * to be used instead. However, the pinctrl driver doesn't support probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * deferring properly. Once this is fixed, this can be switched to a platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) at91rm9200_pmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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