^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Actions Semi S700 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Pathiban Nallathambi <pn@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Saravanan Sekar <sravanhome@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "owl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "owl-composite.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "owl-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "owl-factor.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "owl-fixed-factor.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "owl-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "owl-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "owl-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "owl-reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <dt-bindings/clock/actions,s700-cmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <dt-bindings/reset/actions,s700-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMU_COREPLL (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMU_DEVPLL (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMU_DDRPLL (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMU_NANDPLL (0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMU_DISPLAYPLL (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMU_AUDIOPLL (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMU_TVOUTPLL (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMU_BUSCLK (0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMU_SENSORCLK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMU_LCDCLK (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMU_DSIPLLCLK (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMU_CSICLK (0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMU_DECLK (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMU_SICLK (0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMU_BUSCLK1 (0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMU_HDECLK (0x003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMU_VDECLK (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMU_VCECLK (0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMU_NANDCCLK (0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMU_SD0CLK (0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMU_SD1CLK (0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMU_SD2CLK (0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMU_UART0CLK (0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMU_UART1CLK (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMU_UART2CLK (0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMU_UART3CLK (0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMU_UART4CLK (0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMU_UART5CLK (0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMU_UART6CLK (0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMU_PWM0CLK (0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMU_PWM1CLK (0x007C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMU_PWM2CLK (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMU_PWM3CLK (0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMU_PWM4CLK (0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMU_PWM5CLK (0x008C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CMU_GPU3DCLK (0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMU_CORECTL (0x009C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMU_DEVCLKEN0 (0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMU_DEVCLKEN1 (0x00A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMU_DEVRST0 (0x00A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMU_DEVRST1 (0x00AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMU_USBPLL (0x00B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMU_ETHERNETPLL (0x00B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CMU_CVBSPLL (0x00B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMU_SSTSCLK (0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct clk_pll_table clk_audio_pll_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {0, 45158400}, {1, 49152000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct clk_pll_table clk_cvbs_pll_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {27, 29 * 12000000}, {28, 30 * 12000000}, {29, 31 * 12000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {30, 32 * 12000000}, {31, 33 * 12000000}, {32, 34 * 12000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char *dev_clk_p[] = { "hosc", "dev_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char *i2s_clk_mux_p[] = { "audio_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char *sensor_clk_mux_p[] = { "hosc", "si"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct clk_factor_table sd_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* bit0 ~ 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {24, 1, 25}, {25, 1, 26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* bit8: /128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {280, 1, 25 * 128}, {281, 1, 26 * 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct clk_factor_table lcd_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* bit0 ~ 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* bit8: /7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct clk_div_table hdmia_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0, 1}, {1, 2}, {2, 3}, {3, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {4, 6}, {5, 8}, {6, 12}, {7, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {8, 24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct clk_div_table rmii_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0, 4}, {1, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct clk_factor_table de_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {8, 1, 12}, {0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct clk_factor_table hde_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* composite clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) OWL_MUX_HW(CMU_CSICLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) OWL_MUX_HW(CMU_SICLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) OWL_MUX_HW(CMU_DECLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) OWL_MUX_HW(CMU_HDECLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) OWL_MUX_HW(CMU_VDECLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) OWL_MUX_HW(CMU_VCECLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OWL_MUX_HW(CMU_SD0CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) OWL_MUX_HW(CMU_SD1CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) OWL_MUX_HW(CMU_SD2CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) OWL_MUX_HW(CMU_UART0CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OWL_MUX_HW(CMU_UART1CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) OWL_MUX_HW(CMU_UART2CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) OWL_MUX_HW(CMU_UART3CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) OWL_MUX_HW(CMU_UART4CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) OWL_MUX_HW(CMU_UART5CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) OWL_MUX_HW(CMU_UART6CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) OWL_MUX_HW(CMU_LCDCLK, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* for bluetooth pcm communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 1, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct owl_clk_common *s700_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &clk_core_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &clk_dev_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &clk_ddr_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &clk_nand_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) &clk_display_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &clk_cvbs_pll .common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &clk_audio_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &clk_ethernet_pll.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &clk_cpu.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &clk_dev.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &clk_ahb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &clk_apb.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &clk_dmac.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &clk_noc0_clk_mux.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &clk_noc1_clk_mux.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &clk_hp_clk_mux.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &clk_hp_clk_div.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &clk_noc1_clk_div.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &clk_noc0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &clk_noc1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &clk_sensor_src.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &clk_gpio.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &clk_timer.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &clk_dsi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &clk_csi.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &clk_si.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &clk_de.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &clk_hde.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &clk_vde.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &clk_vce.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &clk_nand.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &clk_sd0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &clk_sd1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &clk_sd2.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &clk_uart0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &clk_uart1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &clk_uart2.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &clk_uart3.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &clk_uart4.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &clk_uart5.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &clk_uart6.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &clk_pwm0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &clk_pwm1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &clk_pwm2.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &clk_pwm3.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) &clk_pwm4.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &clk_pwm5.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &clk_gpu3d.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &clk_i2c0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &clk_i2c1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &clk_i2c2.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &clk_i2c3.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &clk_spi0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &clk_spi1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) &clk_spi2.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &clk_spi3.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) &clk_usb3_480mpll0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) &clk_usb3_480mphy0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &clk_usb3_5gphy.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &clk_usb3_cce.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &clk_lcd.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &clk_hdmi_audio.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &clk_i2srx.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &clk_i2stx.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &clk_sensor0.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &clk_sensor1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &clk_hdmi_dev.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &clk_ethernet.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &clk_rmii_ref.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &clk_usb2h0_pllen.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &clk_usb2h0_phy.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &clk_usb2h0_cce.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) &clk_usb2h1_pllen.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &clk_usb2h1_phy.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &clk_usb2h1_cce.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &clk_tvout.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &clk_thermal_sensor.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &clk_irc_switch.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &clk_pcm1.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct clk_hw_onecell_data s700_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [CLK_CORE_PLL] = &clk_core_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [CLK_CPU] = &clk_cpu.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [CLK_DEV] = &clk_dev.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [CLK_AHB] = &clk_ahb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [CLK_APB] = &clk_apb.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [CLK_DMAC] = &clk_dmac.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [CLK_NOC0] = &clk_noc0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [CLK_NOC1] = &clk_noc1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [CLK_SENOR_SRC] = &clk_sensor_src.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [CLK_GPIO] = &clk_gpio.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [CLK_TIMER] = &clk_timer.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [CLK_DSI] = &clk_dsi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [CLK_CSI] = &clk_csi.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [CLK_SI] = &clk_si.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [CLK_DE] = &clk_de.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [CLK_HDE] = &clk_hde.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [CLK_VDE] = &clk_vde.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [CLK_VCE] = &clk_vce.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [CLK_NAND] = &clk_nand.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [CLK_SD0] = &clk_sd0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [CLK_SD1] = &clk_sd1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [CLK_SD2] = &clk_sd2.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [CLK_UART0] = &clk_uart0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [CLK_UART1] = &clk_uart1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [CLK_UART2] = &clk_uart2.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [CLK_UART3] = &clk_uart3.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [CLK_UART4] = &clk_uart4.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [CLK_UART5] = &clk_uart5.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [CLK_UART6] = &clk_uart6.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [CLK_PWM0] = &clk_pwm0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [CLK_PWM1] = &clk_pwm1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [CLK_PWM2] = &clk_pwm2.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [CLK_PWM3] = &clk_pwm3.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [CLK_PWM4] = &clk_pwm4.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [CLK_PWM5] = &clk_pwm5.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [CLK_GPU3D] = &clk_gpu3d.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [CLK_I2C0] = &clk_i2c0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [CLK_I2C1] = &clk_i2c1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [CLK_I2C2] = &clk_i2c2.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [CLK_I2C3] = &clk_i2c3.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [CLK_SPI0] = &clk_spi0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [CLK_SPI1] = &clk_spi1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [CLK_SPI2] = &clk_spi2.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [CLK_SPI3] = &clk_spi3.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [CLK_LCD] = &clk_lcd.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [CLK_I2SRX] = &clk_i2srx.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [CLK_I2STX] = &clk_i2stx.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [CLK_SENSOR0] = &clk_sensor0.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [CLK_SENSOR1] = &clk_sensor1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [CLK_ETHERNET] = &clk_ethernet.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [CLK_TVOUT] = &clk_tvout.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [CLK_PCM1] = &clk_pcm1.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .num = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct owl_reset_map s700_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) [RESET_DE] = { CMU_DEVRST0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) [RESET_LCD0] = { CMU_DEVRST0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [RESET_DSI] = { CMU_DEVRST0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [RESET_CSI] = { CMU_DEVRST0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) [RESET_SI] = { CMU_DEVRST0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) [RESET_I2C0] = { CMU_DEVRST1, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) [RESET_I2C1] = { CMU_DEVRST1, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [RESET_I2C2] = { CMU_DEVRST1, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [RESET_I2C3] = { CMU_DEVRST1, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [RESET_SPI0] = { CMU_DEVRST1, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) [RESET_SPI1] = { CMU_DEVRST1, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [RESET_SPI2] = { CMU_DEVRST1, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) [RESET_SPI3] = { CMU_DEVRST1, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [RESET_UART0] = { CMU_DEVRST1, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) [RESET_UART1] = { CMU_DEVRST1, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) [RESET_UART2] = { CMU_DEVRST1, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) [RESET_UART3] = { CMU_DEVRST1, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) [RESET_UART4] = { CMU_DEVRST1, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) [RESET_UART5] = { CMU_DEVRST1, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) [RESET_UART6] = { CMU_DEVRST1, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) [RESET_KEY] = { CMU_DEVRST1, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) [RESET_GPIO] = { CMU_DEVRST1, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct owl_clk_desc s700_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .clks = s700_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_clks = ARRAY_SIZE(s700_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .hw_clks = &s700_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .resets = s700_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .num_resets = ARRAY_SIZE(s700_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int s700_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct owl_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct owl_reset *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) desc = &s700_clk_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) owl_clk_regmap_init(pdev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * FIXME: Reset controller registration should be moved to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * common code, once all SoCs of Owl family supports it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reset->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) reset->rcdev.ops = &owl_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) reset->rcdev.nr_resets = desc->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) reset->reset_map = desc->resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) reset->regmap = desc->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(&pdev->dev, "Failed to register reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return owl_clk_probe(&pdev->dev, desc->hw_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct of_device_id s700_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { .compatible = "actions,s700-cmu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct platform_driver s700_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .probe = s700_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .name = "s700-cmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .of_match_table = s700_clk_of_match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int __init s700_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return platform_driver_register(&s700_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) core_initcall(s700_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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