Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Actions Semi Owl S500 SoC clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (c) 2018 LSI-TEC - Caninos Loucos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "owl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "owl-composite.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "owl-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "owl-factor.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "owl-fixed-factor.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "owl-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "owl-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "owl-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "owl-reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <dt-bindings/clock/actions,s500-cmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <dt-bindings/reset/actions,s500-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CMU_COREPLL			(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CMU_DEVPLL			(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CMU_DDRPLL			(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CMU_NANDPLL			(0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CMU_DISPLAYPLL			(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CMU_AUDIOPLL			(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CMU_TVOUTPLL			(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CMU_BUSCLK			(0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CMU_SENSORCLK			(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CMU_LCDCLK			(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CMU_DSICLK			(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CMU_CSICLK			(0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CMU_DECLK			(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CMU_BISPCLK			(0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CMU_BUSCLK1			(0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CMU_VDECLK			(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CMU_VCECLK			(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CMU_NANDCCLK			(0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CMU_SD0CLK			(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CMU_SD1CLK			(0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CMU_SD2CLK			(0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CMU_UART0CLK			(0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CMU_UART1CLK			(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CMU_UART2CLK			(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CMU_PWM4CLK			(0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CMU_PWM5CLK			(0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CMU_PWM0CLK			(0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CMU_PWM1CLK			(0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CMU_PWM2CLK			(0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CMU_PWM3CLK			(0x007C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CMU_USBPLL			(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CMU_ETHERNETPLL			(0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CMU_CVBSPLL			(0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CMU_LENSCLK			(0x008C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CMU_GPU3DCLK			(0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CMU_CORECTL			(0x009C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CMU_DEVCLKEN0			(0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CMU_DEVCLKEN1			(0x00A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CMU_DEVRST0			(0x00A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CMU_DEVRST1			(0x00AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CMU_UART3CLK			(0x00B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CMU_UART4CLK			(0x00B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CMU_UART5CLK			(0x00B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CMU_UART6CLK			(0x00BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CMU_SSCLK			(0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CMU_DIGITALDEBUG		(0x00D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CMU_ANALOGDEBUG			(0x00D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CMU_COREPLLDEBUG		(0x00D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CMU_DEVPLLDEBUG			(0x00DC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CMU_DDRPLLDEBUG			(0x00E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CMU_NANDPLLDEBUG		(0x00E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CMU_DISPLAYPLLDEBUG		(0x00E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CMU_TVOUTPLLDEBUG		(0x00EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CMU_DEEPCOLORPLLDEBUG		(0x00F4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CMU_AUDIOPLL_ETHPLLDEBUG	(0x00F8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CMU_CVBSPLLDEBUG		(0x00FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OWL_S500_COREPLL_DELAY		(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OWL_S500_DDRPLL_DELAY		(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OWL_S500_DEVPLL_DELAY		(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define OWL_S500_NANDPLL_DELAY		(44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define OWL_S500_DISPLAYPLL_DELAY	(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OWL_S500_ETHERNETPLL_DELAY	(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OWL_S500_AUDIOPLL_DELAY		(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct clk_pll_table clk_audio_pll_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ 0, 45158400 }, { 1, 49152000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct clk_factor_table sd_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* bit0 ~ 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ 24, 1, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* bit8: /128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ 280, 1, 25 * 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct clk_factor_table de_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ 8, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk_factor_table hde_factor_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct clk_div_table rmii_ref_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ 0, 4 }, { 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk_div_table std12rate_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk_div_table i2s_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ 8, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clk_div_table nand_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* mux clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* composite clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			OWL_MUX_HW(CMU_VCECLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			OWL_MUX_HW(CMU_VDECLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			OWL_MUX_HW(CMU_BISPCLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			OWL_MUX_HW(CMU_SD0CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			OWL_MUX_HW(CMU_SD1CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			OWL_MUX_HW(CMU_SD2CLK, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			OWL_MUX_HW(CMU_DECLK, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			1, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			1, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			1, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			1, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			OWL_MUX_HW(CMU_UART0CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			OWL_MUX_HW(CMU_UART1CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			OWL_MUX_HW(CMU_UART2CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			OWL_MUX_HW(CMU_UART3CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			OWL_MUX_HW(CMU_UART4CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			OWL_MUX_HW(CMU_UART5CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			OWL_MUX_HW(CMU_UART6CLK, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			CLK_IGNORE_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct owl_clk_common *s500_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	&ethernet_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	&core_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	&ddr_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	&dev_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	&nand_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	&audio_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	&display_pll_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	&dev_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	&timer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	&i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	&i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	&i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	&i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	&uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	&uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	&uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	&uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	&uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	&uart5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	&uart6_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	&pwm0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	&pwm1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	&pwm2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	&pwm3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	&pwm4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	&pwm5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	&sensor0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	&sensor1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	&sd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	&sd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	&sd2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	&bisp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	&ahb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	&ahbprediv_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	&h_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	&spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	&spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	&spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	&spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	&rmii_ref_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	&de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	&de1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	&de2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	&i2srx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	&i2stx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	&hdmia_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	&hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	&vce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	&vde_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	&spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	&nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	&ecc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	&apb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	&dmac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	&gpio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct clk_hw_onecell_data s500_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		[CLK_ETHERNET_PLL]	= &ethernet_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		[CLK_CORE_PLL]		= &core_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		[CLK_DDR_PLL]		= &ddr_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		[CLK_NAND_PLL]		= &nand_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		[CLK_DISPLAY_PLL]	= &display_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		[CLK_DEV_PLL]		= &dev_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		[CLK_AUDIO_PLL]		= &audio_pll_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		[CLK_TIMER]		= &timer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		[CLK_DEV]		= &dev_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		[CLK_DE]		= &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		[CLK_DE1]		= &de1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		[CLK_DE2]		= &de2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		[CLK_I2C0]		= &i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		[CLK_I2C1]		= &i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		[CLK_I2C2]		= &i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		[CLK_I2C3]		= &i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		[CLK_I2SRX]		= &i2srx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		[CLK_I2STX]		= &i2stx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		[CLK_UART0]		= &uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		[CLK_UART1]		= &uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		[CLK_UART2]		= &uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		[CLK_UART3]		= &uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		[CLK_UART4]		= &uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		[CLK_UART5]		= &uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		[CLK_UART6]		= &uart6_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		[CLK_PWM0]		= &pwm0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		[CLK_PWM1]		= &pwm1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		[CLK_PWM2]		= &pwm2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		[CLK_PWM3]		= &pwm3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		[CLK_PWM4]		= &pwm4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		[CLK_PWM5]		= &pwm5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		[CLK_SENSOR0]		= &sensor0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		[CLK_SENSOR1]		= &sensor1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		[CLK_SD0]		= &sd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		[CLK_SD1]		= &sd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		[CLK_SD2]		= &sd2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		[CLK_BISP]		= &bisp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		[CLK_SPI0]		= &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		[CLK_SPI1]		= &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		[CLK_SPI2]		= &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		[CLK_SPI3]		= &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		[CLK_AHB]		= &ahb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		[CLK_H]			= &h_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		[CLK_AHBPREDIV]		= &ahbprediv_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		[CLK_RMII_REF]		= &rmii_ref_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		[CLK_HDMI_AUDIO]	= &hdmia_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		[CLK_HDMI]		= &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		[CLK_VDE]		= &vde_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		[CLK_VCE]		= &vce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		[CLK_SPDIF]		= &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		[CLK_NAND]		= &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		[CLK_ECC]		= &ecc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		[CLK_APB]		= &apb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		[CLK_DMAC]		= &dmac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		[CLK_GPIO]		= &gpio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	.num = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct owl_reset_map s500_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	[RESET_DMAC]	= { CMU_DEVRST0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	[RESET_NORIF]	= { CMU_DEVRST0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	[RESET_DDR]	= { CMU_DEVRST0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	[RESET_NANDC]	= { CMU_DEVRST0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	[RESET_SD0]	= { CMU_DEVRST0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	[RESET_SD1]	= { CMU_DEVRST0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	[RESET_PCM1]	= { CMU_DEVRST0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	[RESET_DE]	= { CMU_DEVRST0, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	[RESET_LCD]	= { CMU_DEVRST0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	[RESET_SD2]	= { CMU_DEVRST0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	[RESET_DSI]	= { CMU_DEVRST0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	[RESET_CSI]	= { CMU_DEVRST0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	[RESET_BISP]	= { CMU_DEVRST0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	[RESET_KEY]	= { CMU_DEVRST0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	[RESET_GPIO]	= { CMU_DEVRST0, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	[RESET_AUDIO]	= { CMU_DEVRST0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	[RESET_PCM0]	= { CMU_DEVRST0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	[RESET_VDE]	= { CMU_DEVRST0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	[RESET_VCE]	= { CMU_DEVRST0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	[RESET_GPU3D]	= { CMU_DEVRST0, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	[RESET_NIC301]	= { CMU_DEVRST0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	[RESET_LENS]	= { CMU_DEVRST0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	[RESET_USB2_0]	= { CMU_DEVRST1, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	[RESET_TVOUT]	= { CMU_DEVRST1, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	[RESET_HDMI]	= { CMU_DEVRST1, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	[RESET_HDCP2TX]	= { CMU_DEVRST1, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	[RESET_UART6]	= { CMU_DEVRST1, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	[RESET_UART0]	= { CMU_DEVRST1, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	[RESET_UART1]	= { CMU_DEVRST1, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	[RESET_UART2]	= { CMU_DEVRST1, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	[RESET_SPI0]	= { CMU_DEVRST1, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	[RESET_SPI1]	= { CMU_DEVRST1, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	[RESET_SPI2]	= { CMU_DEVRST1, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	[RESET_SPI3]	= { CMU_DEVRST1, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	[RESET_I2C0]	= { CMU_DEVRST1, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	[RESET_I2C1]	= { CMU_DEVRST1, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	[RESET_USB3]	= { CMU_DEVRST1, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	[RESET_UART3]	= { CMU_DEVRST1, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	[RESET_UART4]	= { CMU_DEVRST1, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	[RESET_UART5]	= { CMU_DEVRST1, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	[RESET_I2C2]	= { CMU_DEVRST1, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	[RESET_I2C3]	= { CMU_DEVRST1, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	[RESET_CHIPID]	= { CMU_DEVRST1, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	[RESET_USB2_1]	= { CMU_DEVRST1, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct owl_clk_desc s500_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	.clks	    = s500_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	.num_clks   = ARRAY_SIZE(s500_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	.hw_clks    = &s500_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	.resets     = s500_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	.num_resets = ARRAY_SIZE(s500_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int s500_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	struct owl_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	struct owl_reset *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	desc = &s500_clk_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	owl_clk_regmap_init(pdev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	if (!reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	reset->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	reset->rcdev.ops = &owl_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	reset->rcdev.nr_resets = desc->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	reset->reset_map = desc->resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	reset->regmap = desc->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 		dev_err(&pdev->dev, "Failed to register reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	return owl_clk_probe(&pdev->dev, desc->hw_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct of_device_id s500_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	{ .compatible = "actions,s500-cmu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct platform_driver s500_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	.probe = s500_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 		.name = "s500-cmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 		.of_match_table = s500_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int __init s500_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	return platform_driver_register(&s500_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) core_initcall(s500_clk_init);