Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Actions Semi Owl SoCs Reset Management Unit driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "owl-reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static int owl_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			    unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct owl_reset *reset = to_owl_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	const struct owl_reset_map *map = &reset->reset_map[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	return regmap_update_bits(reset->regmap, map->reg, map->bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int owl_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			      unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	struct owl_reset *reset = to_owl_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	const struct owl_reset_map *map = &reset->reset_map[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int owl_reset_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			   unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	owl_reset_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	owl_reset_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int owl_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			    unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct owl_reset *reset = to_owl_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	const struct owl_reset_map *map = &reset->reset_map[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	ret = regmap_read(reset->regmap, map->reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	 * The reset control API expects 0 if reset is not asserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	 * which is the opposite of what our hardware uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return !(map->bit & reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct reset_control_ops owl_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.assert		= owl_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	.deassert	= owl_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.reset		= owl_reset_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.status		= owl_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };