^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // OWL pll clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _OWL_PLL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _OWL_PLL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "owl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OWL_PLL_DEF_DELAY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* last entry should have rate = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_pll_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct owl_pll_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 bfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 min_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 max_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct clk_pll_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct owl_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct owl_pll_hw pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct owl_clk_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) _width, _min_mul, _max_mul, _delay, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .bfreq = _bfreq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .bit_idx = _bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .min_mul = _min_mul, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .max_mul = _max_mul, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .delay = _delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) _shift, _width, _min_mul, _max_mul, _table, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct owl_pll _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) _width, _min_mul, _max_mul, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OWL_PLL_DEF_DELAY, _table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .hw.init = CLK_HW_INIT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &owl_pll_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) _shift, _width, _min_mul, _max_mul, _table, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct owl_pll _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) _width, _min_mul, _max_mul, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OWL_PLL_DEF_DELAY, _table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) &owl_pll_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) _shift, _width, _min_mul, _max_mul, _delay, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct owl_pll _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) _width, _min_mul, _max_mul, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) _delay, _table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &owl_pll_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define mul_mask(m) ((1 << ((m)->width)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct owl_clk_common *common = hw_to_owl_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return container_of(common, struct owl_pll, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern const struct clk_ops owl_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif /* _OWL_PLL_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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