^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // OWL pll clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "owl-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if (mul < pll_hw->min_mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mul = pll_hw->min_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) else if (mul > pll_hw->max_mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mul = pll_hw->max_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return mul &= mul_mask(pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned long _get_table_rate(const struct clk_pll_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct clk_pll_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) for (clkt = table; clkt->rate; clkt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (clkt->val == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return clkt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct clk_pll_table *_get_pll_table(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct clk_pll_table *table, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct clk_pll_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (clkt = table; clkt->rate; clkt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (clkt->rate == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) table = clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } else if (clkt->rate < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) table = clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct owl_pll_hw *pll_hw = &pll->pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct clk_pll_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (pll_hw->table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clkt = _get_pll_table(pll_hw->table, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return clkt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* fixed frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (pll_hw->width == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return pll_hw->bfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mul = owl_pll_calculate_mul(pll_hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return pll_hw->bfreq * mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct owl_pll_hw *pll_hw = &pll->pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const struct owl_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (pll_hw->table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regmap_read(common->regmap, pll_hw->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = val >> pll_hw->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val &= mul_mask(pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return _get_table_rate(pll_hw->table, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* fixed frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pll_hw->width == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return pll_hw->bfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regmap_read(common->regmap, pll_hw->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = val >> pll_hw->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val &= mul_mask(pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return pll_hw->bfreq * val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int owl_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct owl_pll_hw *pll_hw = &pll->pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct owl_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_read(common->regmap, pll_hw->reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return !!(reg & BIT(pll_hw->bit_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void owl_pll_set(const struct owl_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct owl_pll_hw *pll_hw, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_read(common->regmap, pll_hw->reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg |= BIT(pll_hw->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg &= ~BIT(pll_hw->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) regmap_write(common->regmap, pll_hw->reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int owl_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct owl_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) owl_pll_set(common, &pll->pll_hw, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void owl_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct owl_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) owl_pll_set(common, &pll->pll_hw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct owl_pll *pll = hw_to_owl_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct owl_pll_hw *pll_hw = &pll->pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct owl_clk_common *common = &pll->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct clk_pll_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* fixed frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (pll_hw->width == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (pll_hw->table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clkt = _get_pll_table(pll_hw->table, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = clkt->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = owl_pll_calculate_mul(pll_hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regmap_read(common->regmap, pll_hw->reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg &= ~mul_mask(pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg |= val << pll_hw->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regmap_write(common->regmap, pll_hw->reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) udelay(pll_hw->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct clk_ops owl_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .enable = owl_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .disable = owl_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .is_enabled = owl_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .round_rate = owl_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .recalc_rate = owl_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .set_rate = owl_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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