^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // OWL mux clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _OWL_MUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _OWL_MUX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "owl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct owl_mux_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct owl_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct owl_mux_hw mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct owl_clk_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OWL_MUX_HW(_reg, _shift, _width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OWL_MUX(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct owl_mux _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .regmap = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .hw.init = CLK_HW_INIT_PARENTS(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) &owl_mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct owl_clk_common *common = hw_to_owl_clk_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return container_of(common, struct owl_mux, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const struct owl_mux_hw *mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int owl_mux_helper_set_parent(const struct owl_clk_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct owl_mux_hw *mux_hw, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern const struct clk_ops owl_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* _OWL_MUX_H_ */