Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) config HAVE_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	  The <linux/clk.h> calls support software clock gating and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	  thus are a key power management tool on many systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) config CLKDEV_LOOKUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	select HAVE_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) config HAVE_CLK_PREPARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	select HAVE_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	  Select this option when the clock API in <linux/clk.h> is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	  by platform/architecture code. This method is deprecated. Modern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	  code should select COMMON_CLK instead and not define a custom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	  'struct clk'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) menuconfig COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	bool "Common Clock Framework"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	depends on !HAVE_LEGACY_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	select HAVE_CLK_PREPARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	select CLKDEV_LOOKUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	select SRCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	select RATIONAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	  The common clock framework is a single definition of struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	  clk, useful across many platforms, as well as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	  implementation of the clock API in include/linux/clk.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	  Architectures utilizing the common struct clk should select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	  this option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) if COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) config COMMON_CLK_PROCFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	bool "Common Clock PROCFS interface"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	depends on COMMON_CLK && PROC_FS && ARCH_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  Turns on the PROCFS interface for clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) config COMMON_CLK_WM831X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	tristate "Clock driver for WM831x/2x PMICs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	depends on MFD_WM831X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	  Supports the clocking subsystem of the WM831x/2x series of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  PMICs from Wolfson Microelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) source "drivers/clk/versatile/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) config CLK_HSDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	bool "PLL Driver for HSDK platform"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	depends on ARC_SOC_HSDK || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	  This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	  control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) config COMMON_CLK_MAX77686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	tristate "Clock driver for Maxim 77620/77686/77802 MFD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	  This driver supports Maxim 77620/77686/77802 crystal oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	  clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) config COMMON_CLK_MAX9485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	tristate "Maxim 9485 Programmable Clock Generator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	  This driver supports Maxim 9485 Programmable Audio Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) config COMMON_CLK_RK808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	depends on MFD_RK808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	  This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	  Clkout1 is always on, Clkout2 can off by control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) config COMMON_CLK_HI655X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tristate "Clock driver for Hi655x" if EXPERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	depends on (MFD_HI655X_PMIC || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	depends on REGMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	default MFD_HI655X_PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	  This driver supports the hi655x PMIC clock. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	  multi-function device has one fixed-rate oscillator, clocked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	  at 32KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) config COMMON_CLK_SCMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	tristate "Clock driver controlled via SCMI interface"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	  This driver provides support for clocks that are controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	  by firmware that implements the SCMI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	  This driver uses SCMI Message Protocol to interact with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  firmware providing all the clock controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config COMMON_CLK_SCPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tristate "Clock driver controlled via SCPI interface"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	  This driver provides support for clocks that are controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	  by firmware that implements the SCPI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	  This driver uses SCPI Message Protocol to interact with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  firmware providing all the clock controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) config COMMON_CLK_SI5341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	  This driver supports Silicon Labs Si5341 and Si5340 programmable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	  generators. Not all features of these chips are currently supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	  by the driver, in particular it only supports XTAL input. The chip can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	  be pre-programmed to support other configurations and features not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	  implemented in the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) config COMMON_CLK_SI5351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	tristate "Clock driver for SiLabs 5351A/B/C"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	  This driver supports Silicon Labs 5351A/B/C programmable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	  generators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config COMMON_CLK_SI514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	tristate "Clock driver for SiLabs 514 devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	  This driver supports the Silicon Labs 514 programmable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	  generator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) config COMMON_CLK_SI544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	tristate "Clock driver for SiLabs 544 devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	  This driver supports the Silicon Labs 544 programmable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	  generator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) config COMMON_CLK_SI570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tristate "Clock driver for SiLabs 570 and compatible devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	  This driver supports Silicon Labs 570/571/598/599 programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	  clock generators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) config COMMON_CLK_BM1880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	bool "Clock driver for Bitmain BM1880 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	depends on ARCH_BITMAIN || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	default ARCH_BITMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	  This driver supports the clocks on Bitmain BM1880 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) config COMMON_CLK_CDCE706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tristate "Clock driver for TI CDCE706 clock synthesizer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) config COMMON_CLK_CDCE925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	tristate "Clock driver for TI CDCE913/925/937/949 devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	  This driver supports the TI CDCE913/925/937/949 programmable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	  synthesizer. Each chip has different number of PLLs and outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	  For example, the CDCE925 contains two PLLs with spread-spectrum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	  clocking support and five output dividers. The driver only supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	  the following setup, and uses a fixed setting for the output muxes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	  Y1 is derived from the input clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	  Y2 and Y3 derive from PLL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	  Y4 and Y5 derive from PLL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	  Given a target output frequency, the driver will set the PLL and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	  divider to best approximate the desired output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) config COMMON_CLK_CS2000_CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	  If you say yes here you get support for the CS2000 clock multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) config COMMON_CLK_FSL_SAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bool "Clock driver for BCLK of Freescale SAI cores"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	depends on ARCH_LAYERSCAPE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	  This driver supports the Freescale SAI (Synchronous Audio Interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	  to be used as a generic clock output. Some SoCs have restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	  regarding the possible pin multiplexer settings. Eg. on some SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	  two SAI interfaces can only be enabled together. If just one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	  needed, the BCLK pin of the second one can be used as general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	  purpose clock output. Ideally, it can be used to drive an audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	  codec (sometimes known as MCLK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config COMMON_CLK_GEMINI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	bool "Clock driver for Cortina Systems Gemini SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	depends on ARCH_GEMINI || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	select RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	  This driver supports the SoC clocks on the Cortina Systems Gemini
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	  platform, also known as SL3516 or CS3516.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) config COMMON_CLK_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	bool "Clock driver for Aspeed BMC SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	depends on ARCH_ASPEED || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default ARCH_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	select RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	  This driver supports the SoC clocks on the Aspeed BMC platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	  The G4 and G5 series, including the ast2400 and ast2500, are supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	  by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) config COMMON_CLK_S2MPS11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tristate "Clock driver for S2MPS1X/S5M8767 MFD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	depends on MFD_SEC_CORE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	  This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	  clock. These multi-function devices have two (S2MPS14) or three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	  (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) config CLK_TWL6040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	tristate "External McPDM functional clock from twl6040"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	depends on TWL6040_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	  Enable the external functional clock support on OMAP4+ platforms for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	  McPDM. McPDM module is using the external bit clock on the McPDM bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	  as functional clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) config COMMON_CLK_AXI_CLKGEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	tristate "AXI clkgen driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	  FPGAs. It is commonly used in Analog Devices' reference designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) config CLK_QORIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	bool "Clock driver for Freescale QorIQ platforms"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	  This adds the clock driver support for Freescale QorIQ platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	  using common clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) config CLK_LS1028A_PLLDIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)         tristate "Clock driver for LS1028A Display output"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)         depends on ARCH_LAYERSCAPE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)         default ARCH_LAYERSCAPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)         help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)           This driver support the Display output interfaces(LCD, DPHY) pixel clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)           of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)           features of the PLL are currently supported by the driver. By default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)           configured bypass mode with this PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) config COMMON_CLK_XGENE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	bool "Clock driver for APM XGene SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	default ARCH_XGENE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	depends on ARM64 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	  Support for the APM X-Gene SoC reference, PLL, and device clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) config COMMON_CLK_LOCHNAGAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	tristate "Cirrus Logic Lochnagar clock driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	depends on MFD_LOCHNAGAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	  This driver supports the clocking features of the Cirrus Logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	  Lochnagar audio development board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) config COMMON_CLK_NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	select REGMAP_MMIO if ARCH_LPC32XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	select MFD_SYSCON if ARCH_LPC18XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	  Support for clock providers on NXP platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) config COMMON_CLK_PALMAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	tristate "Clock driver for TI Palmas devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	depends on MFD_PALMAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	  This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	  using common clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) config COMMON_CLK_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	tristate "Clock driver for PWMs used as clock outputs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	depends on PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	  Adapter driver so that any PWM output can be (mis)used as clock signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	  at 50% duty cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) config COMMON_CLK_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	def_bool COMMON_CLK && ARCH_PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	  Support for the Marvell PXA SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) config COMMON_CLK_PIC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	def_bool COMMON_CLK && MACH_PIC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) config COMMON_CLK_OXNAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	bool "Clock driver for the OXNAS SoC Family"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	depends on ARCH_OXNAS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	  Support for the OXNAS SoC Family clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) config COMMON_CLK_VC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	tristate "Clock driver for IDT VersaClock 5,6 devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	depends on I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	select REGMAP_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	  This driver supports the IDT VersaClock 5 and VersaClock 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	  programmable clock generators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) config COMMON_CLK_STM32MP157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	def_bool COMMON_CLK && MACH_STM32MP157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	  Support for stm32mp157 SoC family clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) config COMMON_CLK_STM32F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	  Support for stm32f4 and stm32f7 SoC families clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) config COMMON_CLK_STM32H7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	def_bool COMMON_CLK && MACH_STM32H743
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	  Support for stm32h7 SoC family clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) config COMMON_CLK_MMP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	  Support for Marvell MMP2 and MMP3 SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) config COMMON_CLK_MMP2_AUDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)         tristate "Clock driver for MMP2 Audio subsystem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)         depends on COMMON_CLK_MMP2 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)         help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)           This driver supports clocks for Audio subsystem on MMP2 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) config COMMON_CLK_BD718XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	tristate "Clock driver for 32K clk gates on ROHM PMICs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	  This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	  ROHM BD70528 PMICs clock gates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) config COMMON_CLK_FIXED_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	bool "Clock driver for Memory Mapped Fixed values"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	depends on COMMON_CLK && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	  Support for Memory Mapped IO Fixed clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) source "drivers/clk/actions/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) source "drivers/clk/analogbits/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) source "drivers/clk/baikal-t1/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) source "drivers/clk/bcm/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) source "drivers/clk/hisilicon/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) source "drivers/clk/imgtec/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) source "drivers/clk/imx/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) source "drivers/clk/ingenic/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) source "drivers/clk/keystone/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) source "drivers/clk/mediatek/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) source "drivers/clk/meson/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) source "drivers/clk/mvebu/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) source "drivers/clk/qcom/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) source "drivers/clk/renesas/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) source "drivers/clk/rockchip/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) source "drivers/clk/samsung/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) source "drivers/clk/sifive/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) source "drivers/clk/sprd/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) source "drivers/clk/sunxi/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) source "drivers/clk/sunxi-ng/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) source "drivers/clk/tegra/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) source "drivers/clk/ti/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) source "drivers/clk/uniphier/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) source "drivers/clk/x86/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) source "drivers/clk/zynqmp/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) endif