Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/drivers/misc/xillybus_pcie.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011 Xillybus Ltd, http://xillybus.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Driver for the Xillybus FPGA/host framework using PCI Express.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "xillybus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) MODULE_DESCRIPTION("Xillybus driver for PCIe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) MODULE_AUTHOR("Eli Billauer, Xillybus Ltd.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) MODULE_VERSION("1.06");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) MODULE_ALIAS("xillybus_pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PCI_DEVICE_ID_XILLYBUS		0xebeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCI_VENDOR_ID_ACTEL		0x11aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PCI_VENDOR_ID_LATTICE		0x1204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const char xillyname[] = "xillybus_pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static const struct pci_device_id xillyids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_XILLYBUS)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{PCI_DEVICE(PCI_VENDOR_ID_ALTERA, PCI_DEVICE_ID_XILLYBUS)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{PCI_DEVICE(PCI_VENDOR_ID_ACTEL, PCI_DEVICE_ID_XILLYBUS)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{PCI_DEVICE(PCI_VENDOR_ID_LATTICE, PCI_DEVICE_ID_XILLYBUS)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ /* End: all zeroes */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int xilly_pci_direction(int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	case DMA_TO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return PCI_DMA_TODEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	case DMA_FROM_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return PCI_DMA_FROMDEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return PCI_DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void xilly_dma_sync_single_for_cpu_pci(struct xilly_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 					      dma_addr_t dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					      size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					      int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	pci_dma_sync_single_for_cpu(ep->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				    dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				    size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				    xilly_pci_direction(direction));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void xilly_dma_sync_single_for_device_pci(struct xilly_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 						 dma_addr_t dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 						 size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 						 int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pci_dma_sync_single_for_device(ep->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				       dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				       size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 				       xilly_pci_direction(direction));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void xilly_pci_unmap(void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct xilly_mapping *data = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	pci_unmap_single(data->device, data->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			 data->size, data->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	kfree(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * Map either through the PCI DMA mapper or the non_PCI one. Behind the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * scenes exactly the same functions are called with the same parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * but that can change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int xilly_map_single_pci(struct xilly_endpoint *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				void *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				int direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				dma_addr_t *ret_dma_handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int pci_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct xilly_mapping *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	this = kzalloc(sizeof(*this), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (!this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	pci_direction = xilly_pci_direction(direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	addr = pci_map_single(ep->pdev, ptr, size, pci_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (pci_dma_mapping_error(ep->pdev, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		kfree(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	this->device = ep->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	this->dma_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	this->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	this->direction = pci_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	*ret_dma_handle = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return devm_add_action_or_reset(ep->dev, xilly_pci_unmap, this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct xilly_endpoint_hardware pci_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.hw_sync_sgl_for_cpu = xilly_dma_sync_single_for_cpu_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.hw_sync_sgl_for_device = xilly_dma_sync_single_for_device_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.map_single = xilly_map_single_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int xilly_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		       const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct xilly_endpoint *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	endpoint = xillybus_init_endpoint(pdev, &pdev->dev, &pci_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (!endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pci_set_drvdata(pdev, endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		dev_err(endpoint->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			"pcim_enable_device() failed. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* L0s has caused packet drops. No power saving, thank you. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		dev_err(endpoint->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			"Incorrect BAR configuration. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	rc = pcim_iomap_regions(pdev, 0x01, xillyname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(endpoint->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			"pcim_iomap_regions() failed. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	endpoint->registers = pcim_iomap_table(pdev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Set up a single MSI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (pci_enable_msi(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(endpoint->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			"Failed to enable MSI interrupts. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	rc = devm_request_irq(&pdev->dev, pdev->irq, xillybus_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			      xillyname, endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_err(endpoint->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			"Failed to register MSI handler. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * Some (old and buggy?) hardware drops 64-bit addressed PCIe packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * even when the PCIe driver claims that a 64-bit mask is OK. On the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * other hand, on some architectures, 64-bit addressing is mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * So go for the 64-bit mask only when failing is the other option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		endpoint->dma_using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		endpoint->dma_using_dac = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		dev_err(endpoint->dev, "Failed to set DMA mask. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return xillybus_endpoint_discovery(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void xilly_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct xilly_endpoint *endpoint = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	xillybus_endpoint_remove(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(pci, xillyids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct pci_driver xillybus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.name = xillyname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.id_table = xillyids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.probe = xilly_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.remove = xilly_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) module_pci_driver(xillybus_driver);