^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/misc/xillybus.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Xillybus Ltd, http://xillybus.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Header file for the Xillybus FPGA/host framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __XILLYBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __XILLYBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct xilly_endpoint_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct xilly_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int end_offset; /* Counting elements, not bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct xilly_idt_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned char *chandesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char *idt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * wr_* buffers are those consumed by read(), since the FPGA writes to them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * and vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct xilly_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct xilly_endpoint *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int log2_element_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int seekable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int num_wr_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int wr_buf_size; /* In bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int wr_fpga_buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int wr_host_buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int wr_host_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int wr_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int wr_ready; /* Significant only when wr_empty == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int wr_sleepy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int wr_eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int wr_hangup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spinlock_t wr_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mutex wr_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) wait_queue_head_t wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) wait_queue_head_t wr_ready_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int wr_ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int wr_synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int wr_allow_partial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int wr_exclusive_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int wr_supports_nonempty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int num_rd_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int rd_buf_size; /* In bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int rd_fpga_buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int rd_host_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int rd_host_buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int rd_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) spinlock_t rd_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mutex rd_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) wait_queue_head_t rd_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int rd_ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int rd_allow_partial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int rd_synchronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int rd_exclusive_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct delayed_work rd_workitem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char rd_leftovers[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct xilly_endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * One of pdev and dev is always NULL, and the other is a valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * pointer, depending on the type of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct xilly_endpoint_hardware *ephw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct list_head ep_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __iomem void *registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mutex register_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) wait_queue_head_t ep_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Channels and message handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct cdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int num_channels; /* EXCLUDING message buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct xilly_channel **channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int msg_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int failed_messages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int idtlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 *msgbuf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dma_addr_t msgbuf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int msg_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct xilly_endpoint_hardware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_addr_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) size_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dma_addr_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) size_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int (*map_single)(struct xilly_endpoint *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) size_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dma_addr_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct xilly_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irqreturn_t xillybus_isr(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct xilly_endpoint_hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *ephw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* __XILLYBUS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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