Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Timer device implementation for SGI UV platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2009 Silicon Graphics, Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mmtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/posix-timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/genapic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/uv/uv_hub.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/uv/bios.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/uv/uv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) MODULE_AUTHOR("Dimitri Sivanich <sivanich@sgi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) MODULE_DESCRIPTION("SGI UV Memory Mapped RTC Timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* name of the device, usually in /dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define UV_MMTIMER_NAME "mmtimer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define UV_MMTIMER_DESC "SGI UV Memory Mapped RTC Timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define UV_MMTIMER_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static long uv_mmtimer_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 						unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int uv_mmtimer_mmap(struct file *file, struct vm_area_struct *vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * Period in femtoseconds (10^-15 s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static unsigned long uv_mmtimer_femtoperiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static const struct file_operations uv_mmtimer_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.mmap =	uv_mmtimer_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.unlocked_ioctl = uv_mmtimer_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.llseek = noop_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * uv_mmtimer_ioctl - ioctl interface for /dev/uv_mmtimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @file: file structure for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * @cmd: command to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @arg: optional argument to command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * Executes the command specified by @cmd.  Returns 0 for success, < 0 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * Valid commands:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * %MMTIMER_GETOFFSET - Should return the offset (relative to the start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * of the page where the registers are mapped) for the counter in question.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * %MMTIMER_GETRES - Returns the resolution of the clock in femto (10^-15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * %MMTIMER_GETFREQ - Copies the frequency of the clock in Hz to the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * specified by @arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * %MMTIMER_GETBITS - Returns the number of bits in the clock's counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * %MMTIMER_MMAPAVAIL - Returns 1 if registers can be mmap'd into userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * %MMTIMER_GETCOUNTER - Gets the current value in the counter and places it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * in the address specified by @arg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static long uv_mmtimer_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 						unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case MMTIMER_GETOFFSET:	/* offset of the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 * Starting with HUB rev 2.0, the UV RTC register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * replicated across all cachelines of it's own page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * This allows faster simultaneous reads from a given socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * The offset returned is in 64 bit units.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (uv_get_min_hub_revision_id() == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			ret = ((uv_blade_processor_id() * L1_CACHE_BYTES) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					PAGE_SIZE) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case MMTIMER_GETRES: /* resolution of the clock in 10^-15 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (copy_to_user((unsigned long __user *)arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				&uv_mmtimer_femtoperiod, sizeof(unsigned long)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case MMTIMER_GETFREQ: /* frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (copy_to_user((unsigned long __user *)arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				&sn_rtc_cycles_per_second,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				sizeof(unsigned long)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case MMTIMER_GETBITS: /* number of bits in the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		ret = hweight64(UVH_RTC_REAL_TIME_CLOCK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case MMTIMER_MMAPAVAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case MMTIMER_GETCOUNTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (copy_to_user((unsigned long __user *)arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				(unsigned long *)uv_local_mmr_address(UVH_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				sizeof(unsigned long)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * uv_mmtimer_mmap - maps the clock's registers into userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * @file: file structure for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * @vma: VMA to map the registers into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * Calls remap_pfn_range() to map the clock's registers into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * the calling process' address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int uv_mmtimer_mmap(struct file *file, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long uv_mmtimer_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (vma->vm_flags & VM_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (PAGE_SIZE > (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	uv_mmtimer_addr = UV_LOCAL_MMR_BASE | UVH_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	uv_mmtimer_addr &= ~(PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	uv_mmtimer_addr &= 0xfffffffffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (remap_pfn_range(vma, vma->vm_start, uv_mmtimer_addr >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					PAGE_SIZE, vma->vm_page_prot)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		printk(KERN_ERR "remap_pfn_range failed in uv_mmtimer_mmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct miscdevice uv_mmtimer_miscdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	MISC_DYNAMIC_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	UV_MMTIMER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	&uv_mmtimer_fops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * uv_mmtimer_init - device initialization routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * Does initial setup for the uv_mmtimer device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int __init uv_mmtimer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!is_uv_system()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		printk(KERN_ERR "%s: Hardware unsupported\n", UV_MMTIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * Sanity check the cycles/sec variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (sn_rtc_cycles_per_second < 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		printk(KERN_ERR "%s: unable to determine clock frequency\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		       UV_MMTIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	uv_mmtimer_femtoperiod = ((unsigned long)1E15 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				sn_rtc_cycles_per_second / 2) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				sn_rtc_cycles_per_second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (misc_register(&uv_mmtimer_miscdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		printk(KERN_ERR "%s: failed to register device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		       UV_MMTIMER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	printk(KERN_INFO "%s: v%s, %ld MHz\n", UV_MMTIMER_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		UV_MMTIMER_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		sn_rtc_cycles_per_second/(unsigned long)1E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) module_init(uv_mmtimer_init);