^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Device Driver for the Infineon Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SLD 9630 TT 1.1 and SLB 9635 TT 1.2 Trusted Platform Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Specifications at www.trustedcomputinggroup.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005, Marcel Selhorst <tpmdd@selhorst.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sirrix AG - security technologies <tpmdd@sirrix.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Applied Data Security Group, Ruhr-University Bochum, Germany
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Project-Homepage: http://www.trust.rub.de/projects/linux-device-driver-infineon-tpm/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "tpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Infineon specific definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* maximum number of WTX-packages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TPM_MAX_WTX_PACKAGES 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* msleep-Time for WTX-packages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TPM_WTX_MSLEEP_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* msleep-Time --> Interval to check status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TPM_MSLEEP_TIME 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* gives number of max. msleep()-calls before throwing timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TPM_MAX_TRIES 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TPM_INFINEON_DEV_VEN_VALUE 0x15D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TPM_INF_IO_PORT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TPM_INF_IO_MEM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TPM_INF_ADDR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TPM_INF_DATA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct tpm_inf_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int iotype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *mem_base; /* MMIO ioremap'd addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long map_base; /* phys MMIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long map_size; /* MMIO region size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int index_off; /* index register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int data_regs; /* Data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int config_port; /* IO Port config index reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int config_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct tpm_inf_dev tpm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void tpm_data_out(unsigned char data, unsigned char offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (tpm_dev.iotype == TPM_INF_IO_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) outb(data, tpm_dev.data_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writeb(data, tpm_dev.mem_base + tpm_dev.data_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline unsigned char tpm_data_in(unsigned char offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (tpm_dev.iotype == TPM_INF_IO_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return inb(tpm_dev.data_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return readb(tpm_dev.mem_base + tpm_dev.data_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline void tpm_config_out(unsigned char data, unsigned char offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (tpm_dev.iotype == TPM_INF_IO_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) outb(data, tpm_dev.config_port + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writeb(data, tpm_dev.mem_base + tpm_dev.index_off + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline unsigned char tpm_config_in(unsigned char offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (tpm_dev.iotype == TPM_INF_IO_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return inb(tpm_dev.config_port + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return readb(tpm_dev.mem_base + tpm_dev.index_off + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* TPM header definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum infineon_tpm_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) TPM_VL_VER = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) TPM_VL_CHANNEL_CONTROL = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) TPM_VL_CHANNEL_PERSONALISATION = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) TPM_VL_CHANNEL_TPM = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TPM_VL_CONTROL = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) TPM_INF_NAK = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) TPM_CTRL_WTX = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) TPM_CTRL_WTX_ABORT = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) TPM_CTRL_WTX_ABORT_ACK = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) TPM_CTRL_ERROR = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) TPM_CTRL_CHAININGACK = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) TPM_CTRL_CHAINING = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TPM_CTRL_DATA = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) TPM_CTRL_DATA_CHA = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) TPM_CTRL_DATA_CHA_ACK = 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum infineon_tpm_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) WRFIFO = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RDFIFO = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) STAT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CMD = 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum infineon_tpm_command_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CMD_DIS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CMD_LP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CMD_RES = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CMD_IRQC = 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum infineon_tpm_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) STAT_XFE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) STAT_LPA = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) STAT_FOK = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) STAT_TOK = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) STAT_IRQA = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) STAT_RDA = 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* some outgoing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum infineon_tpm_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CHIP_ID1 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CHIP_ID2 = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) TPM_DAR = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RESET_LP_IRQC_DISABLE = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ENABLE_REGISTER_PAIR = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) IOLIMH = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) IOLIML = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DISABLE_REGISTER_PAIR = 0xAA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IDVENL = 0xF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IDVENH = 0xF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IDPDL = 0xF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IDPDH = 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int number_of_wtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int empty_fifo(struct tpm_chip *chip, int clear_wrfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int check = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (clear_wrfifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < 4096; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) status = tpm_data_in(WRFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (status == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (check == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) check++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Note: The values which are currently in the FIFO of the TPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) are thrown away since there is no usage for them. Usually,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) this has nothing to say, since the TPM will give its answer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) immediately or will be aborted anyway, so the data here is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) usually garbage and useless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) We have to clean this, because the next communication with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) the TPM would be rubbish, if there is still some old data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) in the Read FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) status = tpm_data_in(RDFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) status = tpm_data_in(STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (i == TPM_MAX_TRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } while ((status & (1 << STAT_RDA)) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int wait(struct tpm_chip *chip, int wait_for_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < TPM_MAX_TRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) status = tpm_data_in(STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* check the status-register if wait_for_bit is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (status & 1 << wait_for_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tpm_msleep(TPM_MSLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (i == TPM_MAX_TRIES) { /* timeout occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (wait_for_bit == STAT_XFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(&chip->dev, "Timeout in wait(STAT_XFE)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (wait_for_bit == STAT_RDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(&chip->dev, "Timeout in wait(STAT_RDA)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void wait_and_send(struct tpm_chip *chip, u8 sendbyte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wait(chip, STAT_XFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) tpm_data_out(sendbyte, WRFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Note: WTX means Waiting-Time-Extension. Whenever the TPM needs more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) calculation time, it sends a WTX-package, which has to be acknowledged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) or aborted. This usually occurs if you are hammering the TPM with key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) creation. Set the maximum number of WTX-packages in the definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) above, if the number is reached, the waiting-time will be denied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) and the TPM command has to be resend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void tpm_wtx(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) number_of_wtx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_info(&chip->dev, "Granting WTX (%02d / %02d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) number_of_wtx, TPM_MAX_WTX_PACKAGES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) wait_and_send(chip, TPM_VL_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) wait_and_send(chip, TPM_CTRL_WTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wait_and_send(chip, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wait_and_send(chip, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tpm_msleep(TPM_WTX_MSLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void tpm_wtx_abort(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_info(&chip->dev, "Aborting WTX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) wait_and_send(chip, TPM_VL_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) wait_and_send(chip, TPM_CTRL_WTX_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wait_and_send(chip, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wait_and_send(chip, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) number_of_wtx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tpm_msleep(TPM_WTX_MSLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int tpm_inf_recv(struct tpm_chip *chip, u8 * buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) number_of_wtx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) recv_begin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* start receiving header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = wait(chip, STAT_RDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) buf[i] = tpm_data_in(RDFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (buf[0] != TPM_VL_VER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(&chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "Wrong transport protocol implementation!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (buf[1] == TPM_CTRL_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* size of the data received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) size = ((buf[2] << 8) | buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wait(chip, STAT_RDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) buf[i] = tpm_data_in(RDFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if ((size == 0x6D00) && (buf[1] == 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(&chip->dev, "Error handling on vendor layer!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) buf[i] = buf[i + 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) size = size - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (buf[1] == TPM_CTRL_WTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_info(&chip->dev, "WTX-package received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (number_of_wtx < TPM_MAX_WTX_PACKAGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tpm_wtx(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto recv_begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tpm_wtx_abort(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) goto recv_begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (buf[1] == TPM_CTRL_WTX_ABORT_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_info(&chip->dev, "WTX-abort acknowledged\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (buf[1] == TPM_CTRL_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(&chip->dev, "ERROR-package received:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (buf[4] == TPM_INF_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(&chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "-> Negative acknowledgement"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) " - retransmit command!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int tpm_inf_send(struct tpm_chip *chip, u8 * buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 count_high, count_low, count_4, count_3, count_2, count_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Disabling Reset, LP and IRQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tpm_data_out(RESET_LP_IRQC_DISABLE, CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = empty_fifo(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(&chip->dev, "Timeout while clearing FIFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = wait(chip, STAT_XFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) count_4 = (count & 0xff000000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) count_3 = (count & 0x00ff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) count_2 = (count & 0x0000ff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) count_1 = (count & 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) count_high = ((count + 6) & 0xffffff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) count_low = ((count + 6) & 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Sending Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) wait_and_send(chip, TPM_VL_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) wait_and_send(chip, TPM_CTRL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) wait_and_send(chip, count_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) wait_and_send(chip, count_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Sending Data Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) wait_and_send(chip, TPM_VL_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) wait_and_send(chip, TPM_VL_CHANNEL_TPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) wait_and_send(chip, count_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) wait_and_send(chip, count_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) wait_and_send(chip, count_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) wait_and_send(chip, count_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Sending Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) wait_and_send(chip, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void tpm_inf_cancel(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) Since we are using the legacy mode to communicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) with the TPM, we have no cancel functions, but have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) a workaround for interrupting the TPM through WTX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static u8 tpm_inf_status(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return tpm_data_in(STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct tpm_class_ops tpm_inf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .recv = tpm_inf_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .send = tpm_inf_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .cancel = tpm_inf_cancel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .status = tpm_inf_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .req_complete_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .req_complete_val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct pnp_device_id tpm_inf_pnp_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Infineon TPMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {"IFX0101", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {"IFX0102", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {"", 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DEVICE_TABLE(pnp, tpm_inf_pnp_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int tpm_inf_pnp_probe(struct pnp_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const struct pnp_device_id *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 iol, ioh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int vendorid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int productid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const char *chipname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tpm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* read IO-ports through PnP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tpm_dev.iotype = TPM_INF_IO_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tpm_dev.config_port = pnp_port_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tpm_dev.config_size = pnp_port_len(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tpm_dev.data_regs = pnp_port_start(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tpm_dev.data_size = pnp_port_len(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if ((tpm_dev.data_size < 4) || (tpm_dev.config_size < 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_info(&dev->dev, "Found %s with ID %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev->name, dev_id->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!((tpm_dev.data_regs >> 8) & 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* publish my base address and request region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (request_region(tpm_dev.data_regs, tpm_dev.data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "tpm_infineon0") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (request_region(tpm_dev.config_port, tpm_dev.config_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "tpm_infineon0") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) release_region(tpm_dev.data_regs, tpm_dev.data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else if (pnp_mem_valid(dev, 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) !(pnp_mem_flags(dev, 0) & IORESOURCE_DISABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tpm_dev.iotype = TPM_INF_IO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tpm_dev.map_base = pnp_mem_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tpm_dev.map_size = pnp_mem_len(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_info(&dev->dev, "Found %s with ID %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev->name, dev_id->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* publish my base address and request region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (request_mem_region(tpm_dev.map_base, tpm_dev.map_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "tpm_infineon0") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tpm_dev.mem_base = ioremap(tpm_dev.map_base, tpm_dev.map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (tpm_dev.mem_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) release_mem_region(tpm_dev.map_base, tpm_dev.map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * The only known MMIO based Infineon TPM system provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * a single large mem region with the device config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * registers at the default TPM_ADDR. The data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * seem like they could be placed anywhere within the MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * region, but lets just put them at zero offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tpm_dev.index_off = TPM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tpm_dev.data_regs = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* query chip for its vendor, its version number a.s.o. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tpm_config_out(ENABLE_REGISTER_PAIR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tpm_config_out(IDVENL, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) vendorid[1] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tpm_config_out(IDVENH, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) vendorid[0] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tpm_config_out(IDPDL, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) productid[1] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tpm_config_out(IDPDH, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) productid[0] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tpm_config_out(CHIP_ID1, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) version[1] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tpm_config_out(CHIP_ID2, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) version[0] = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) switch ((productid[0] << 8) | productid[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) chipname = " (SLD 9630 TT 1.1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) chipname = " (SLB 9635 TT 1.2)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) chipname = " (unknown chip)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if ((vendorid[0] << 8 | vendorid[1]) == (TPM_INFINEON_DEV_VEN_VALUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* configure TPM with IO-ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tpm_config_out(IOLIMH, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tpm_config_out((tpm_dev.data_regs >> 8) & 0xff, TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tpm_config_out(IOLIML, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tpm_config_out((tpm_dev.data_regs & 0xff), TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* control if IO-ports are set correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tpm_config_out(IOLIMH, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ioh = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tpm_config_out(IOLIML, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) iol = tpm_config_in(TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if ((ioh << 8 | iol) != tpm_dev.data_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "Could not set IO-data registers to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tpm_dev.data_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* activate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tpm_config_out(TPM_DAR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tpm_config_out(0x01, TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tpm_config_out(DISABLE_REGISTER_PAIR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* disable RESET, LP and IRQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tpm_data_out(RESET_LP_IRQC_DISABLE, CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Finally, we're done, print some infos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_info(&dev->dev, "TPM found: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "config base 0x%lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "data base 0x%lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "chip version 0x%02x%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "vendor id 0x%x%x (Infineon), "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "product id 0x%02x%02x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tpm_dev.iotype == TPM_INF_IO_PORT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) tpm_dev.config_port :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) tpm_dev.map_base + tpm_dev.index_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tpm_dev.iotype == TPM_INF_IO_PORT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tpm_dev.data_regs :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tpm_dev.map_base + tpm_dev.data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) version[0], version[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) vendorid[0], vendorid[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) productid[0], productid[1], chipname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) chip = tpmm_chip_alloc(&dev->dev, &tpm_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (IS_ERR(chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rc = PTR_ERR(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto err_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rc = tpm_chip_register(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) goto err_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto err_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) err_release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (tpm_dev.iotype == TPM_INF_IO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) release_region(tpm_dev.data_regs, tpm_dev.data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) release_region(tpm_dev.config_port, tpm_dev.config_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) iounmap(tpm_dev.mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) release_mem_region(tpm_dev.map_base, tpm_dev.map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err_last:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void tpm_inf_pnp_remove(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct tpm_chip *chip = pnp_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) tpm_chip_unregister(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (tpm_dev.iotype == TPM_INF_IO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) release_region(tpm_dev.data_regs, tpm_dev.data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) release_region(tpm_dev.config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tpm_dev.config_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) iounmap(tpm_dev.mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) release_mem_region(tpm_dev.map_base, tpm_dev.map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int tpm_inf_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Re-configure TPM after suspending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tpm_config_out(ENABLE_REGISTER_PAIR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) tpm_config_out(IOLIMH, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) tpm_config_out((tpm_dev.data_regs >> 8) & 0xff, TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tpm_config_out(IOLIML, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tpm_config_out((tpm_dev.data_regs & 0xff), TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* activate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) tpm_config_out(TPM_DAR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) tpm_config_out(0x01, TPM_INF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) tpm_config_out(DISABLE_REGISTER_PAIR, TPM_INF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* disable RESET, LP and IRQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) tpm_data_out(RESET_LP_IRQC_DISABLE, CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return tpm_pm_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static SIMPLE_DEV_PM_OPS(tpm_inf_pm, tpm_pm_suspend, tpm_inf_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct pnp_driver tpm_inf_pnp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "tpm_inf_pnp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .id_table = tpm_inf_pnp_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .probe = tpm_inf_pnp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .remove = tpm_inf_pnp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .pm = &tpm_inf_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) module_pnp_driver(tpm_inf_pnp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_AUTHOR("Marcel Selhorst <tpmdd@sirrix.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MODULE_DESCRIPTION("Driver for Infineon TPM SLD 9630 TT 1.1 / SLB 9635 TT 1.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_VERSION("1.9.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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