^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Maintained by: <tpmdd-devel@lists.sourceforge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This device driver implements the TPM interface as defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the TCG CRB 2.0 TPM specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rculist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "tpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACPI_SIG_TPM2 "TPM2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TPM_CRB_MAX_RESOURCES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const guid_t crb_acpi_start_guid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) GUID_INIT(0x6BBF6CAB, 0x5463, 0x4714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum crb_defaults {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CRB_ACPI_START_REVISION_ID = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CRB_ACPI_START_INDEX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum crb_loc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CRB_LOC_CTRL_RELINQUISH = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum crb_loc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CRB_LOC_STATE_LOC_ASSIGNED = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CRB_LOC_STATE_TPM_REG_VALID_STS = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum crb_ctrl_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CRB_CTRL_REQ_CMD_READY = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CRB_CTRL_REQ_GO_IDLE = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum crb_ctrl_sts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CRB_CTRL_STS_ERROR = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CRB_CTRL_STS_TPM_IDLE = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum crb_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CRB_START_INVOKE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum crb_cancel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CRB_CANCEL_INVOKE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct crb_regs_head {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 loc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 loc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 loc_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 reserved2[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u64 intf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u64 ctrl_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct crb_regs_tail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 ctrl_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 ctrl_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 ctrl_cancel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 ctrl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 ctrl_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 ctrl_int_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 ctrl_cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 ctrl_cmd_pa_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 ctrl_cmd_pa_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 ctrl_rsp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 ctrl_rsp_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum crb_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CRB_DRV_STS_COMPLETE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct crb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct crb_regs_head __iomem *regs_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct crb_regs_tail __iomem *regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 __iomem *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 __iomem *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 smc_func_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct tpm2_crb_smc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 interrupt_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 op_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 smc_func_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ktime_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ktime_t stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) stop = ktime_add(start, ms_to_ktime(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ((ioread32(reg) & mask) == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) usleep_range(50, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } while (ktime_before(ktime_get(), stop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ((ioread32(reg) & mask) == value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * __crb_go_idle - request tpm crb device to go the idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @dev: crb device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @priv: crb private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Write CRB_CTRL_REQ_GO_IDLE to TPM_CRB_CTRL_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * The device should respond within TIMEOUT_C by clearing the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Anyhow, we do not wait here as a consequent CMD_READY request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * will be handled correctly even if idle was not completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The function does nothing for devices with ACPI-start method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * or SMC-start method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int __crb_go_idle(struct device *dev, struct crb_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if ((priv->sm == ACPI_TPM2_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) iowrite32(CRB_CTRL_REQ_GO_IDLE, &priv->regs_t->ctrl_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!crb_wait_for_reg_32(&priv->regs_t->ctrl_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CRB_CTRL_REQ_GO_IDLE/* mask */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0, /* value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TPM2_TIMEOUT_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_warn(dev, "goIdle timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int crb_go_idle(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct device *dev = &chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct crb_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return __crb_go_idle(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * __crb_cmd_ready - request tpm crb device to enter ready state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @dev: crb device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @priv: crb private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Write CRB_CTRL_REQ_CMD_READY to TPM_CRB_CTRL_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * and poll till the device acknowledge it by clearing the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * The device should respond within TIMEOUT_C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * The function does nothing for devices with ACPI-start method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * or SMC-start method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Return: 0 on success -ETIME on timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __crb_cmd_ready(struct device *dev, struct crb_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if ((priv->sm == ACPI_TPM2_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) iowrite32(CRB_CTRL_REQ_CMD_READY, &priv->regs_t->ctrl_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!crb_wait_for_reg_32(&priv->regs_t->ctrl_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CRB_CTRL_REQ_CMD_READY /* mask */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0, /* value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TPM2_TIMEOUT_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_warn(dev, "cmdReady timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int crb_cmd_ready(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device *dev = &chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct crb_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return __crb_cmd_ready(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int __crb_request_locality(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct crb_priv *priv, int loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 value = CRB_LOC_STATE_LOC_ASSIGNED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) CRB_LOC_STATE_TPM_REG_VALID_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!priv->regs_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) iowrite32(CRB_LOC_CTRL_REQUEST_ACCESS, &priv->regs_h->loc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, value, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TPM2_TIMEOUT_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int crb_request_locality(struct tpm_chip *chip, int loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return __crb_request_locality(&chip->dev, priv, loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int __crb_relinquish_locality(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct crb_priv *priv, int loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 mask = CRB_LOC_STATE_LOC_ASSIGNED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CRB_LOC_STATE_TPM_REG_VALID_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 value = CRB_LOC_STATE_TPM_REG_VALID_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!priv->regs_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iowrite32(CRB_LOC_CTRL_RELINQUISH, &priv->regs_h->loc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, mask, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) TPM2_TIMEOUT_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int crb_relinquish_locality(struct tpm_chip *chip, int loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return __crb_relinquish_locality(&chip->dev, priv, loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static u8 crb_status(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 sts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if ((ioread32(&priv->regs_t->ctrl_start) & CRB_START_INVOKE) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CRB_START_INVOKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sts |= CRB_DRV_STS_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* A sanity check that the upper layer wants to get at least the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * as that is the minimum size for any TPM response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (count < TPM_HEADER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* If this bit is set, according to the spec, the TPM is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * unrecoverable condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ioread32(&priv->regs_t->ctrl_sts) & CRB_CTRL_STS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Read the first 8 bytes in order to get the length of the response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * We read exactly a quad word in order to make sure that the remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * reads will be aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) memcpy_fromio(buf, priv->rsp, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) expected = be32_to_cpup((__be32 *)&buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (expected > count || expected < TPM_HEADER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) memcpy_fromio(&buf[8], &priv->rsp[8], expected - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int crb_do_acpi_start(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) &crb_acpi_start_guid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CRB_ACPI_START_REVISION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CRB_ACPI_START_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rc = obj->integer.value == 0 ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ACPI_FREE(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * This is a TPM Command Response Buffer start method that invokes a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Secure Monitor Call to requrest the firmware to execute or cancel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * a TPM 2.0 command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int tpm_crb_smc_start(struct device *dev, unsigned long func_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) arm_smccc_smc(func_id, 0, 0, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (res.a0 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FW_BUG "tpm_crb_smc_start() returns res.a0 = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) res.a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int tpm_crb_smc_start(struct device *dev, unsigned long func_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(dev, FW_BUG "tpm_crb: incorrect start method\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Zero the cancel register so that the next command will not get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * canceled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) iowrite32(0, &priv->regs_t->ctrl_cancel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (len > priv->cmd_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(&chip->dev, "invalid command count value %zd %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) len, priv->cmd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memcpy_toio(priv->cmd, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Make sure that cmd is populated before issuing start. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * report only ACPI start but in practice seems to require both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * CRB start, hence invoking CRB start method if hid == MSFT0101.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if ((priv->sm == ACPI_TPM2_COMMAND_BUFFER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (priv->sm == ACPI_TPM2_MEMORY_MAPPED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (!strcmp(priv->hid, "MSFT0101")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) iowrite32(CRB_START_INVOKE, &priv->regs_t->ctrl_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((priv->sm == ACPI_TPM2_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rc = crb_do_acpi_start(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) iowrite32(CRB_START_INVOKE, &priv->regs_t->ctrl_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rc = tpm_crb_smc_start(&chip->dev, priv->smc_func_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void crb_cancel(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) iowrite32(CRB_CANCEL_INVOKE, &priv->regs_t->ctrl_cancel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (((priv->sm == ACPI_TPM2_START_METHOD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) crb_do_acpi_start(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&chip->dev, "ACPI Start failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct crb_priv *priv = dev_get_drvdata(&chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 cancel = ioread32(&priv->regs_t->ctrl_cancel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct tpm_class_ops tpm_crb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = TPM_OPS_AUTO_STARTUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .status = crb_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .recv = crb_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .send = crb_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .cancel = crb_cancel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .req_canceled = crb_req_canceled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .go_idle = crb_go_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .cmd_ready = crb_cmd_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .request_locality = crb_request_locality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .relinquish_locality = crb_relinquish_locality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .req_complete_mask = CRB_DRV_STS_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .req_complete_val = CRB_DRV_STS_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int crb_check_resource(struct acpi_resource *ares, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct resource *iores_array = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct resource_win win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct resource *res = &(win.res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (acpi_dev_resource_memory(ares, res) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) acpi_dev_resource_address_space(ares, &win)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (i = 0; i < TPM_CRB_MAX_RESOURCES + 1; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (resource_type(iores_array + i) != IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) iores_array[i] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) iores_array[i].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void __iomem *crb_map_res(struct device *dev, struct resource *iores,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void __iomem **iobase_ptr, u64 start, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct resource new_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .start = start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .end = start + size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Detect a 64 bit address on a 32 bit system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (start != new_res.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return (void __iomem *) ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return devm_ioremap_resource(dev, &new_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!*iobase_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *iobase_ptr = devm_ioremap_resource(dev, iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(*iobase_ptr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return *iobase_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return *iobase_ptr + (new_res.start - iores->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Work around broken BIOSs that return inconsistent values from the ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * region vs the registers. Trust the ACPI region. Such broken systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * probably cannot send large TPM commands since the buffer will be truncated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static u64 crb_fixup_cmd_size(struct device *dev, struct resource *io_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u64 start, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (io_res->start > start || io_res->end < start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (start + size - 1 <= io_res->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) FW_BUG "ACPI region does not cover the entire command/response buffer. %pr vs %llx %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) io_res, start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return io_res->end - start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int crb_map_io(struct acpi_device *device, struct crb_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct acpi_table_tpm2 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct list_head acpi_resource_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct resource iores_array[TPM_CRB_MAX_RESOURCES + 1] = { {0} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *iobase_array[TPM_CRB_MAX_RESOURCES] = {NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct device *dev = &device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void __iomem **iobase_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 pa_high, pa_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u64 cmd_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __le64 __rsp_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u64 rsp_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 rsp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) INIT_LIST_HEAD(&acpi_resource_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = acpi_dev_get_resources(device, &acpi_resource_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) crb_check_resource, iores_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) acpi_dev_free_resource_list(&acpi_resource_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (resource_type(iores_array) != IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } else if (resource_type(iores_array + TPM_CRB_MAX_RESOURCES) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_warn(dev, "TPM2 ACPI table defines too many memory resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) memset(iores_array + TPM_CRB_MAX_RESOURCES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0, sizeof(*iores_array));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) iores_array[TPM_CRB_MAX_RESOURCES].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) iores = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) iobase_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; resource_type(iores_array + i) == IORESOURCE_MEM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (buf->control_address >= iores_array[i].start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) buf->control_address + sizeof(struct crb_regs_tail) - 1 <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) iores_array[i].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) iores = iores_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) iobase_ptr = iobase_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) priv->regs_t = crb_map_res(dev, iores, iobase_ptr, buf->control_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sizeof(struct crb_regs_tail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (IS_ERR(priv->regs_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return PTR_ERR(priv->regs_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* The ACPI IO region starts at the head area and continues to include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * the control area, as one nice sane region except for some older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * stuff that puts the control area outside the ACPI IO region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if ((priv->sm == ACPI_TPM2_COMMAND_BUFFER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) (priv->sm == ACPI_TPM2_MEMORY_MAPPED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (iores &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) buf->control_address == iores->start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) sizeof(*priv->regs_h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->regs_h = *iobase_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_warn(dev, FW_BUG "Bad ACPI memory layout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = __crb_request_locality(dev, priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * PTT HW bug w/a: wake up the device to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * possibly not retained registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = __crb_cmd_ready(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto out_relinquish_locality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pa_high = ioread32(&priv->regs_t->ctrl_cmd_pa_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pa_low = ioread32(&priv->regs_t->ctrl_cmd_pa_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cmd_pa = ((u64)pa_high << 32) | pa_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cmd_size = ioread32(&priv->regs_t->ctrl_cmd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) iores = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) iobase_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (i = 0; iores_array[i].end; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (cmd_pa >= iores_array[i].start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cmd_pa <= iores_array[i].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) iores = iores_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) iobase_ptr = iobase_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cmd_size = crb_fixup_cmd_size(dev, iores, cmd_pa, cmd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_dbg(dev, "cmd_hi = %X cmd_low = %X cmd_size %X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pa_high, pa_low, cmd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) priv->cmd = crb_map_res(dev, iores, iobase_ptr, cmd_pa, cmd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (IS_ERR(priv->cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = PTR_ERR(priv->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) memcpy_fromio(&__rsp_pa, &priv->regs_t->ctrl_rsp_pa, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rsp_pa = le64_to_cpu(__rsp_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rsp_size = ioread32(&priv->regs_t->ctrl_rsp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) iores = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) iobase_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (i = 0; resource_type(iores_array + i) == IORESOURCE_MEM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (rsp_pa >= iores_array[i].start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rsp_pa <= iores_array[i].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) iores = iores_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) iobase_ptr = iobase_array + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rsp_size = crb_fixup_cmd_size(dev, iores, rsp_pa, rsp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (cmd_pa != rsp_pa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) priv->rsp = crb_map_res(dev, iores, iobase_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) rsp_pa, rsp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = PTR_ERR_OR_ZERO(priv->rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* According to the PTP specification, overlapping command and response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * buffer sizes must be identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (cmd_size != rsp_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(dev, FW_BUG "overlapping command and response buffer sizes are not identical");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) priv->rsp = priv->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) priv->cmd_size = cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __crb_go_idle(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) out_relinquish_locality:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __crb_relinquish_locality(dev, priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int crb_acpi_add(struct acpi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct acpi_table_tpm2 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct crb_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct tpm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct device *dev = &device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct tpm2_crb_smc *crb_smc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) status = acpi_get_table(ACPI_SIG_TPM2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) (struct acpi_table_header **) &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ACPI_FAILURE(status) || buf->header.length < sizeof(*buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Should the FIFO driver handle this? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) sm = buf->start_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (sm == ACPI_TPM2_MEMORY_MAPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (buf->header.length < (sizeof(*buf) + sizeof(*crb_smc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) FW_BUG "TPM2 ACPI table has wrong size %u for start method type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) buf->header.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) crb_smc = ACPI_ADD_PTR(struct tpm2_crb_smc, buf, sizeof(*buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) priv->smc_func_id = crb_smc->smc_func_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) priv->sm = sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) priv->hid = acpi_device_hid(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rc = crb_map_io(device, priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) chip = tpmm_chip_alloc(dev, &tpm_crb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (IS_ERR(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return PTR_ERR(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_set_drvdata(&chip->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) chip->acpi_dev_handle = device->handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) chip->flags = TPM_CHIP_FLAG_TPM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return tpm_chip_register(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int crb_acpi_remove(struct acpi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct device *dev = &device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct tpm_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tpm_chip_unregister(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const struct dev_pm_ops crb_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SET_SYSTEM_SLEEP_PM_OPS(tpm_pm_suspend, tpm_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const struct acpi_device_id crb_device_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {"MSFT0101", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {"", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_DEVICE_TABLE(acpi, crb_device_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct acpi_driver crb_acpi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .name = "tpm_crb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .ids = crb_device_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .add = crb_acpi_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .remove = crb_acpi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pm = &crb_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) module_acpi_driver(crb_acpi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("TPM2 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_VERSION("0.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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