^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Leendert van Doorn <leendert@watson.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Dave Safford <safford@watson.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Reiner Sailer <sailer@watson.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Kylene Hall <kjhall@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Device driver for TCG/TCPA TPM (trusted platform module).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Specifications at www.trustedcomputinggroup.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tpm_eventlog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "tpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TPM_MAX_ORDINAL 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Array with one entry per ordinal defining the maximum amount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * of time the chip could take to return the result. The ordinal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * designation of short, medium or long is defined in a table in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * TCG Specification TPM Main Part 2 TPM Structures Section 17. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * values of the SHORT, MEDIUM, and LONG durations are retrieved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * from the chip during initialization with a call to tpm_get_timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const u8 tpm1_ordinal_duration[TPM_MAX_ORDINAL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TPM_UNDEFINED, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) TPM_UNDEFINED, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) TPM_SHORT, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) TPM_MEDIUM, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) TPM_SHORT, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) TPM_SHORT, /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) TPM_MEDIUM, /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TPM_SHORT, /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) TPM_MEDIUM, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) TPM_SHORT, /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) TPM_MEDIUM, /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) TPM_UNDEFINED, /* 55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) TPM_MEDIUM, /* 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) TPM_MEDIUM, /* 65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) TPM_SHORT, /* 70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TPM_UNDEFINED, /* 75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TPM_LONG, /* 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) TPM_UNDEFINED, /* 85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) TPM_SHORT, /* 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) TPM_UNDEFINED, /* 95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TPM_MEDIUM, /* 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) TPM_UNDEFINED, /* 105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TPM_SHORT, /* 110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) TPM_SHORT, /* 115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TPM_LONG, /* 120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) TPM_SHORT, /* 125 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) TPM_SHORT, /* 130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TPM_UNDEFINED, /* 135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TPM_SHORT, /* 140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) TPM_UNDEFINED, /* 145 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) TPM_SHORT, /* 150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TPM_UNDEFINED, /* 155 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) TPM_SHORT, /* 160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) TPM_UNDEFINED, /* 165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) TPM_LONG, /* 170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TPM_UNDEFINED, /* 175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) TPM_MEDIUM, /* 180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) TPM_MEDIUM, /* 185 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) TPM_UNDEFINED, /* 190 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) TPM_UNDEFINED, /* 195 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TPM_SHORT, /* 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TPM_SHORT, /* 205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TPM_MEDIUM, /* 210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TPM_UNDEFINED, /* 215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) TPM_SHORT, /* 220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TPM_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) TPM_UNDEFINED, /* 225 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TPM_SHORT, /* 230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) TPM_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) TPM_UNDEFINED, /* 235 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TPM_SHORT, /* 240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) TPM_UNDEFINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) TPM_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * tpm1_calc_ordinal_duration() - calculate the maximum command duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @chip: TPM chip to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @ordinal: TPM command ordinal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * The function returns the maximum amount of time the chip could take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * to return the result for a particular ordinal in jiffies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Return: A maximal duration time for an ordinal in jiffies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long tpm1_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int duration_idx = TPM_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int duration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * We only have a duration table for protected commands, where the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * 16 bits are 0. For the few other ordinals the fallback will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ordinal < TPM_MAX_ORDINAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) duration_idx = tpm1_ordinal_duration[ordinal];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (duration_idx != TPM_UNDEFINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) duration = chip->duration[duration_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (duration <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 2 * 60 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TPM_ORD_STARTUP 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TPM_ST_CLEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * tpm_startup() - turn on the TPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @chip: TPM chip to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Normally the firmware should start the TPM. This function is provided as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * workaround if this does not happen. A legal case for this could be for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * example when a TPM emulator is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Return: same as tpm_transmit_cmd()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int tpm1_startup(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_info(&chip->dev, "starting up the TPM manually\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_STARTUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tpm_buf_append_u16(&buf, TPM_ST_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to start the TPM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int tpm1_get_timeouts(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cap_t cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long timeout_old[4], timeout_chip[4], timeout_eff[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long durations[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ssize_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rc = tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sizeof(cap.timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (rc == TPM_ERR_INVALID_POSTINIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (tpm1_startup(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rc = tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "attempting to determine the timeouts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sizeof(cap.timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&chip->dev, "A TPM error (%zd) occurred attempting to determine the timeouts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) timeout_old[0] = jiffies_to_usecs(chip->timeout_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) timeout_old[1] = jiffies_to_usecs(chip->timeout_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) timeout_old[2] = jiffies_to_usecs(chip->timeout_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) timeout_old[3] = jiffies_to_usecs(chip->timeout_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) timeout_chip[0] = be32_to_cpu(cap.timeout.a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) timeout_chip[1] = be32_to_cpu(cap.timeout.b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) timeout_chip[2] = be32_to_cpu(cap.timeout.c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) timeout_chip[3] = be32_to_cpu(cap.timeout.d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memcpy(timeout_eff, timeout_chip, sizeof(timeout_eff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Provide ability for vendor overrides of timeout values in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * of misreporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (chip->ops->update_timeouts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) chip->ops->update_timeouts(chip, timeout_eff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!chip->timeout_adjusted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Restore default if chip reported 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < ARRAY_SIZE(timeout_eff); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (timeout_eff[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) timeout_eff[i] = timeout_old[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) chip->timeout_adjusted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (timeout_eff[0] != 0 && timeout_eff[0] < 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* timeouts in msec rather usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for (i = 0; i != ARRAY_SIZE(timeout_eff); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) timeout_eff[i] *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) chip->timeout_adjusted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Report adjusted timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (chip->timeout_adjusted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_info(&chip->dev, HW_ERR "Adjusting reported timeouts: A %lu->%luus B %lu->%luus C %lu->%luus D %lu->%luus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) timeout_chip[0], timeout_eff[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) timeout_chip[1], timeout_eff[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) timeout_chip[2], timeout_eff[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) timeout_chip[3], timeout_eff[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) chip->timeout_a = usecs_to_jiffies(timeout_eff[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) chip->timeout_b = usecs_to_jiffies(timeout_eff[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) chip->timeout_c = usecs_to_jiffies(timeout_eff[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) chip->timeout_d = usecs_to_jiffies(timeout_eff[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rc = tpm1_getcap(chip, TPM_CAP_PROP_TIS_DURATION, &cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "attempting to determine the durations",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sizeof(cap.duration));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) chip->duration[TPM_SHORT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) usecs_to_jiffies(be32_to_cpu(cap.duration.tpm_short));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) chip->duration[TPM_MEDIUM] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) usecs_to_jiffies(be32_to_cpu(cap.duration.tpm_medium));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) chip->duration[TPM_LONG] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) usecs_to_jiffies(be32_to_cpu(cap.duration.tpm_long));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) chip->duration[TPM_LONG_LONG] = 0; /* not used under 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Provide the ability for vendor overrides of duration values in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * of misreporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (chip->ops->update_durations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) chip->ops->update_durations(chip, durations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (chip->duration_adjusted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_info(&chip->dev, HW_ERR "Adjusting reported durations.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) chip->duration[TPM_SHORT] = durations[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) chip->duration[TPM_MEDIUM] = durations[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chip->duration[TPM_LONG] = durations[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* The Broadcom BCM0102 chipset in a Dell Latitude D820 gets the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * value wrong and apparently reports msecs rather than usecs. So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * fix up the resulting too-small TPM_SHORT value to make things work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * We also scale the TPM_MEDIUM and -_LONG values by 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (chip->duration[TPM_SHORT] < (HZ / 100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) chip->duration[TPM_SHORT] = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) chip->duration[TPM_MEDIUM] *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) chip->duration[TPM_LONG] *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) chip->duration_adjusted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_info(&chip->dev, "Adjusting TPM timeout parameters.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define TPM_ORD_PCR_EXTEND 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int tpm1_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, const u8 *hash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const char *log_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_PCR_EXTEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) tpm_buf_append_u32(&buf, pcr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tpm_buf_append(&buf, hash, TPM_DIGEST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) rc = tpm_transmit_cmd(chip, &buf, TPM_DIGEST_SIZE, log_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define TPM_ORD_GET_CAP 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ssize_t tpm1_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const char *desc, size_t min_cap_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_GET_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (subcap_id == TPM_CAP_VERSION_1_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) subcap_id == TPM_CAP_VERSION_1_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tpm_buf_append_u32(&buf, subcap_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tpm_buf_append_u32(&buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (subcap_id == TPM_CAP_FLAG_PERM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) subcap_id == TPM_CAP_FLAG_VOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) tpm_buf_append_u32(&buf, TPM_CAP_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tpm_buf_append_u32(&buf, TPM_CAP_PROP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tpm_buf_append_u32(&buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) tpm_buf_append_u32(&buf, subcap_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rc = tpm_transmit_cmd(chip, &buf, min_cap_length, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *cap = *(cap_t *)&buf.data[TPM_HEADER_SIZE + 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXPORT_SYMBOL_GPL(tpm1_getcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TPM_ORD_GET_RANDOM 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct tpm1_get_random_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __be32 rng_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 rng_data[TPM_MAX_RNG_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * tpm1_get_random() - get random bytes from the TPM's RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * @chip: a &struct tpm_chip instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * @dest: destination buffer for the random bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * @max: the maximum number of bytes to write to @dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * * number of bytes read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * * -errno (positive TPM return codes are masked to -EIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int tpm1_get_random(struct tpm_chip *chip, u8 *dest, size_t max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct tpm1_get_random_out *out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 num_bytes = min_t(u32, max, TPM_MAX_RNG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 recd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_GET_RANDOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) tpm_buf_append_u32(&buf, num_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rc = tpm_transmit_cmd(chip, &buf, sizeof(out->rng_data_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "attempting get random");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (rc > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) out = (struct tpm1_get_random_out *)&buf.data[TPM_HEADER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) recd = be32_to_cpu(out->rng_data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (recd > num_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (tpm_buf_length(&buf) < TPM_HEADER_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) sizeof(out->rng_data_len) + recd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) memcpy(dest, out->rng_data, recd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dest += recd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) total += recd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) num_bytes -= recd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tpm_buf_reset(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_GET_RANDOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } while (retries-- && total < max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) rc = total ? (int)total : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define TPM_ORD_PCRREAD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int tpm1_pcr_read(struct tpm_chip *chip, u32 pcr_idx, u8 *res_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_PCRREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tpm_buf_append_u32(&buf, pcr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rc = tpm_transmit_cmd(chip, &buf, TPM_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "attempting to read a pcr value");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (tpm_buf_length(&buf) < TPM_DIGEST_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memcpy(res_buf, &buf.data[TPM_HEADER_SIZE], TPM_DIGEST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define TPM_ORD_CONTINUE_SELFTEST 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * tpm_continue_selftest() - run TPM's selftest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @chip: TPM chip to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Returns 0 on success, < 0 in case of fatal error or a value > 0 representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * a TPM error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int tpm1_continue_selftest(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_CONTINUE_SELFTEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rc = tpm_transmit_cmd(chip, &buf, 0, "continue selftest");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * tpm1_do_selftest - have the TPM continue its selftest and wait until it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * can receive further commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @chip: TPM chip to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Returns 0 on success, < 0 in case of fatal error or a value > 0 representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * a TPM error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int tpm1_do_selftest(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int delay_msec = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned long duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8 dummy[TPM_DIGEST_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) duration = tpm1_calc_ordinal_duration(chip, TPM_ORD_CONTINUE_SELFTEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) loops = jiffies_to_msecs(duration) / delay_msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rc = tpm1_continue_selftest(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (rc == TPM_ERR_INVALID_POSTINIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) chip->flags |= TPM_CHIP_FLAG_ALWAYS_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_info(&chip->dev, "TPM not ready (%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* This may fail if there was no TPM driver during a suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * cycle; some may return 10 (BAD_ORDINAL), others 28 (FAILEDSELFTEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Attempt to read a PCR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) rc = tpm1_pcr_read(chip, 0, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Some buggy TPMs will not respond to tpm_tis_ready() for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * around 300ms while the self test is ongoing, keep trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * until the self test duration expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (rc == -ETIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_info(&chip->dev, HW_ERR "TPM command timed out during continue self test");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tpm_msleep(delay_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (rc == TPM_ERR_DISABLED || rc == TPM_ERR_DEACTIVATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_info(&chip->dev, "TPM is disabled/deactivated (0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* TPM is disabled and/or deactivated; driver can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * proceed and TPM does handle commands for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * suspend/resume correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (rc != TPM_WARN_DOING_SELFTEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tpm_msleep(delay_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) } while (--loops > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) EXPORT_SYMBOL_GPL(tpm1_do_selftest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * tpm1_auto_startup - Perform the standard automatic TPM initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @chip: TPM chip to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Returns 0 on success, < 0 in case of fatal error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int tpm1_auto_startup(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) rc = tpm1_get_timeouts(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rc = tpm1_do_selftest(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(&chip->dev, "TPM self test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (rc > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TPM_ORD_SAVESTATE 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * tpm1_pm_suspend() - pm suspend handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * @chip: TPM chip to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * @tpm_suspend_pcr: flush pcr for buggy TPM chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * The functions saves the TPM state to be restored on resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * * 0 on success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * * < 0 on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int tpm1_pm_suspend(struct tpm_chip *chip, u32 tpm_suspend_pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u8 dummy_hash[TPM_DIGEST_SIZE] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct tpm_buf buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned int try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* for buggy tpm, flush pcrs with extend to selected dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (tpm_suspend_pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) rc = tpm1_pcr_extend(chip, tpm_suspend_pcr, dummy_hash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "extending dummy pcr before suspend");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rc = tpm_buf_init(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_SAVESTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* now do the actual savestate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) for (try = 0; try < TPM_RETRY; try++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rc = tpm_transmit_cmd(chip, &buf, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * If the TPM indicates that it is too busy to respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * this command then retry before giving up. It can take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * several seconds for this TPM to be ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * This can happen if the TPM has already been sent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * SaveState command before the driver has loaded. TCG 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * specification states that any communication after SaveState
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * may cause the TPM to invalidate previously saved state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (rc != TPM_WARN_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tpm_msleep(TPM_TIMEOUT_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tpm_buf_reset(&buf, TPM_TAG_RQU_COMMAND, TPM_ORD_SAVESTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(&chip->dev, "Error (%d) sending savestate before suspend\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) else if (try > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_warn(&chip->dev, "TPM savestate took %dms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) try * TPM_TIMEOUT_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) tpm_buf_destroy(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * tpm1_get_pcr_allocation() - initialize the allocated bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @chip: TPM chip to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * The function initializes the SHA1 allocated bank to extend PCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * * 0 on success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * * < 0 on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int tpm1_get_pcr_allocation(struct tpm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) chip->allocated_banks = kcalloc(1, sizeof(*chip->allocated_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!chip->allocated_banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) chip->allocated_banks[0].alg_id = TPM_ALG_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) chip->allocated_banks[0].digest_size = hash_digest_size[HASH_ALGO_SHA1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) chip->allocated_banks[0].crypto_id = HASH_ALGO_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) chip->nr_allocated_banks = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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