Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef	_CM4040_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define	_CM4040_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define	CM_MAX_DEV		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define	DEVICE_NAME		"cmx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define	MODULE_NAME		"cm4040_cs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define REG_OFFSET_BULK_OUT      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define REG_OFFSET_BULK_IN       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define REG_OFFSET_BUFFER_STATUS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REG_OFFSET_SYNC_CONTROL  2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BSR_BULK_IN_FULL  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BSR_BULK_OUT_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCR_HOST_TO_READER_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SCR_ABORT                0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCR_EN_NOTIFY            0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCR_ACK_NOTIFY           0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCR_READER_TO_HOST_DONE  0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCR_HOST_TO_READER_DONE  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCR_PULSE_INTERRUPT      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCR_POWER_DOWN           0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define  CMD_PC_TO_RDR_ICCPOWERON       0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define  CMD_PC_TO_RDR_GETSLOTSTATUS    0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define  CMD_PC_TO_RDR_ICCPOWEROFF      0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define  CMD_PC_TO_RDR_SECURE           0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define  CMD_PC_TO_RDR_GETPARAMETERS    0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define  CMD_PC_TO_RDR_RESETPARAMETERS  0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define  CMD_PC_TO_RDR_SETPARAMETERS    0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define  CMD_PC_TO_RDR_XFRBLOCK         0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define  CMD_PC_TO_RDR_ESCAPE           0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define  CMD_PC_TO_RDR_ICCCLOCK         0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define  CMD_PC_TO_RDR_TEST_SECURE      0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define  CMD_PC_TO_RDR_OK_SECURE        0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define  CMD_RDR_TO_PC_SLOTSTATUS         0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define  CMD_RDR_TO_PC_DATABLOCK          0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define  CMD_RDR_TO_PC_PARAMETERS         0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define  CMD_RDR_TO_PC_ESCAPE             0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define  CMD_RDR_TO_PC_OK_SECURE          0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif	/* _CM4040_H_ */