Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* linux/drivers/char/pc8736x_gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    National Semiconductor PC8736x GPIO driver.  Allows a user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)    process to play with the GPIO pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    adapted from linux/drivers/char/scx200_gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)    Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/nsc_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DEVNAME "pc8736x_gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int major;		/* default to dynamic major */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_param(major, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_PARM_DESC(major, "Major device number");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static DEFINE_MUTEX(pc8736x_gpio_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static unsigned pc8736x_gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static u8 pc8736x_gpio_shadow[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SIO_BASE1       0x2E	/* 1st command-reg to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SIO_BASE2       0x4E	/* alt command-reg to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SIO_SID		0x20	/* SuperI/O ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SIO_SID_PC87365	0xe5	/* Expected value in ID Register for PC87365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SIO_SID_PC87366	0xe9	/* Expected value in ID Register for PC87366 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SIO_CF1		0x21	/* chip config, bit0 is chip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PC8736X_GPIO_RANGE	16 /* ioaddr range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PC8736X_GPIO_CT		32 /* minors matching 4 8 bit ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SIO_UNIT_SEL	0x7	/* unit select reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SIO_UNIT_ACT	0x30	/* unit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SIO_GPIO_UNIT	0x7	/* unit number of GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SIO_VLM_UNIT	0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SIO_TMS_UNIT	0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* config-space addrs to read/write each unit's runtime addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SIO_BASE_HADDR		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SIO_BASE_LADDR		0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* GPIO config-space pin-control addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SIO_GPIO_PIN_SELECT	0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SIO_GPIO_PIN_CONFIG     0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SIO_GPIO_PIN_EVENT      0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static unsigned char superio_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static unsigned char selected_device = 0xFF;	/* bogus start val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* GPIO port runtime access, functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int port_offset[] = { 0, 4, 8, 10 };	/* non-uniform offsets ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* static int event_capable[] = { 1, 1, 0, 0 };   ports 2,3 are hobbled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PORT_OUT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PORT_IN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PORT_EVT_EN	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PORT_EVT_STST	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct platform_device *pdev;  /* use in dev_*() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline void superio_outb(int addr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	outb_p(addr, superio_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	outb_p(val, superio_cmd + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static inline int superio_inb(int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	outb_p(addr, superio_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return inb_p(superio_cmd + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int pc8736x_superio_present(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* try the 2 possible values, read a hardware reg to verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	superio_cmd = SIO_BASE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	id = superio_inb(SIO_SID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (id == SIO_SID_PC87365 || id == SIO_SID_PC87366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return superio_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	superio_cmd = SIO_BASE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	id = superio_inb(SIO_SID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (id == SIO_SID_PC87365 || id == SIO_SID_PC87366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return superio_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void device_select(unsigned devldn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	superio_outb(SIO_UNIT_SEL, devldn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	selected_device = devldn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void select_pin(unsigned iminor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* select GPIO port/pin from device minor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	device_select(SIO_GPIO_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	superio_outb(SIO_GPIO_PIN_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		     ((iminor << 1) & 0xF0) | (iminor & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 					    u32 func_slct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 config, new_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mutex_lock(&pc8736x_gpio_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	device_select(SIO_GPIO_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	select_pin(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* read current config value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	config = superio_inb(func_slct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* set new config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	new_config = (config & mask) | bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	superio_outb(func_slct, new_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mutex_unlock(&pc8736x_gpio_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return pc8736x_gpio_configure_fn(index, mask, bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					 SIO_GPIO_PIN_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int pc8736x_gpio_get(unsigned minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int port, bit, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	port = minor >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	bit = minor & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	val >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	val &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void pc8736x_gpio_set(unsigned minor, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int port, bit, curval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	minor &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	port = minor >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bit = minor & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		pc8736x_gpio_base + port_offset[port] + PORT_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		curval, bit, (curval & ~(1 << bit)), val, (val << bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	val = (curval & ~(1 << bit)) | (val << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		" %2x -> %2x\n", minor, port, bit, curval, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	pc8736x_gpio_shadow[port] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int pc8736x_gpio_current(unsigned minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	int port, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	minor &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	port = minor >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	bit = minor & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void pc8736x_gpio_change(unsigned index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct nsc_gpio_ops pc8736x_gpio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.gpio_config	= pc8736x_gpio_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.gpio_dump	= nsc_gpio_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.gpio_get	= pc8736x_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.gpio_set	= pc8736x_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.gpio_change	= pc8736x_gpio_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.gpio_current	= pc8736x_gpio_current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int pc8736x_gpio_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned m = iminor(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	file->private_data = &pc8736x_gpio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	dev_dbg(&pdev->dev, "open %d\n", m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (m >= PC8736X_GPIO_CT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return nonseekable_open(inode, file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct file_operations pc8736x_gpio_fileops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.owner	= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.open	= pc8736x_gpio_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.write	= nsc_gpio_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.read	= nsc_gpio_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.llseek = no_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void __init pc8736x_init_shadow(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* read the current values driven on the GPIO signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	for (port = 0; port < 4; ++port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pc8736x_gpio_shadow[port]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		    = inb_p(pc8736x_gpio_base + port_offset[port]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			    + PORT_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct cdev pc8736x_gpio_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __init pc8736x_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	dev_t devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pdev = platform_device_alloc(DEVNAME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	rc = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto undo_platform_dev_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (!pc8736x_superio_present()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_err(&pdev->dev, "no device found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto undo_platform_dev_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	pc8736x_gpio_ops.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* Verify that chip and it's GPIO unit are both enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	   My BIOS does this, so I take minimum action here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rc = superio_inb(SIO_CF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!(rc & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		dev_err(&pdev->dev, "device not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		goto undo_platform_dev_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	device_select(SIO_GPIO_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!superio_inb(SIO_UNIT_ACT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dev_err(&pdev->dev, "GPIO unit not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		goto undo_platform_dev_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* read the GPIO unit base addr that chip responds to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			     | superio_inb(SIO_BASE_LADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_err(&pdev->dev, "GPIO ioport %x busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			pc8736x_gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		goto undo_platform_dev_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		devid = MKDEV(major, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		major = MAJOR(devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		goto undo_request_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		major = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	pc8736x_init_shadow();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* ignore minor errs, and succeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) undo_request_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) undo_platform_dev_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	platform_device_del(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) undo_platform_dev_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __exit pc8736x_gpio_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dev_dbg(&pdev->dev, "cleanup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	cdev_del(&pc8736x_gpio_cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) module_init(pc8736x_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) module_exit(pc8736x_gpio_cleanup);