^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tp3780i.c -- board driver for 3780i on ThinkPads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written By: Mike Sullivan IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 10/23/2000 - Alpha Release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * First release to the public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "smapi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "mwavedd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "tp3780i.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "3780i.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "mwavepub.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static unsigned short s_ausThinkpadIrqToField[16] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0xFFFF, 0xFFFF, 0xFFFF, 0x0001, 0x0002, 0x0003, 0xFFFF, 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0xFFFF, 0xFFFF, 0x0005, 0x0006, 0xFFFF, 0xFFFF, 0xFFFF, 0x0007 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned short s_ausThinkpadDmaToField[8] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 0x0001, 0x0002, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0003, 0x0004 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static unsigned short s_numIrqs = 16, s_numDmas = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void EnableSRAM(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DSP_GPIO_OUTPUT_DATA_15_8 rGpioOutputData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DSP_GPIO_DRIVER_ENABLE_15_8 rGpioDriverEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DSP_GPIO_MODE_15_8 rGpioMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM, entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MKWORD(rGpioMode) = ReadMsaCfg(DSP_GpioModeControl_15_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rGpioMode.GpioMode10 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) WriteMsaCfg(DSP_GpioModeControl_15_8, MKWORD(rGpioMode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MKWORD(rGpioDriverEnable) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rGpioDriverEnable.Enable10 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rGpioDriverEnable.Mask10 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) WriteMsaCfg(DSP_GpioDriverEnable_15_8, MKWORD(rGpioDriverEnable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MKWORD(rGpioOutputData) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rGpioOutputData.Latch10 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) rGpioOutputData.Mask10 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) WriteMsaCfg(DSP_GpioOutputData_15_8, MKWORD(rGpioOutputData));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PRINTK_1(TRACE_TP3780I, "tp3780i::EnableSRAM exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static irqreturn_t UartInterrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PRINTK_3(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "tp3780i::UartInterrupt entry irq %x dev_id %p\n", irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static irqreturn_t DspInterrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DSP_3780I_CONFIG_SETTINGS *pSettings = &pDrvData->rBDData.rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned short usIPCSource = 0, usIsolationMask, usPCNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PRINTK_3(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "tp3780i::DspInterrupt entry irq %x dev_id %p\n", irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (dsp3780I_GetIPCSource(usDspBaseIO, &usIPCSource) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "tp3780i::DspInterrupt, return from dsp3780i_GetIPCSource, usIPCSource %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) usIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) usIsolationMask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (usPCNum = 1; usPCNum <= 16; usPCNum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (usIPCSource & usIsolationMask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) usIPCSource &= ~usIsolationMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PRINTK_3(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "tp3780i::DspInterrupt usPCNum %x usIPCSource %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) usPCNum, usIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (pDrvData->IPCs[usPCNum - 1].usIntCount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pDrvData->IPCs[usPCNum - 1].usIntCount = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "tp3780i::DspInterrupt usIntCount %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pDrvData->IPCs[usPCNum - 1].usIntCount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (pDrvData->IPCs[usPCNum - 1].bIsEnabled == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "tp3780i::DspInterrupt, waking up usPCNum %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) usPCNum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wake_up_interruptible(&pDrvData->IPCs[usPCNum - 1].ipc_wait_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "tp3780i::DspInterrupt, no one waiting for IPC %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) usPCNum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (usIPCSource == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* try next IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) usIsolationMask = usIsolationMask << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PRINTK_1(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "tp3780i::DspInterrupt, return false from dsp3780i_GetIPCSource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PRINTK_1(TRACE_TP3780I, "tp3780i::DspInterrupt exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pBDData->bDSPEnabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pSettings->bInterruptClaimed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) retval = smapi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_InitializeBoardData: Error: SMAPI is not available on this machine\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (mwave_3780i_irq || mwave_3780i_io || mwave_uart_irq || mwave_uart_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) retval = smapi_set_DSP_cfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_InitializeBoardData exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int tp3780I_Cleanup(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "tp3780i::tp3780I_Cleanup entry and exit pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SMAPI_DSP_SETTINGS rSmapiInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "tp3780i::tp3780I_CalcResources entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (smapi_query_DSP_cfg(&rSmapiInfo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Could not query DSP config. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ( rSmapiInfo.usDspIRQ == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) || ( rSmapiInfo.usDspBaseIO == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) || ( rSmapiInfo.usUartIRQ == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) || ( rSmapiInfo.usUartBaseIO == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_CalcResources: Error: Illegal resource setting. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pSettings->bDSPEnabled = (rSmapiInfo.bDSPEnabled && rSmapiInfo.bDSPPresent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pSettings->bModemEnabled = rSmapiInfo.bModemEnabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pSettings->usDspIrq = rSmapiInfo.usDspIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pSettings->usDspDma = rSmapiInfo.usDspDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pSettings->usDspBaseIO = rSmapiInfo.usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pSettings->usUartIrq = rSmapiInfo.usUartIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pSettings->usUartBaseIO = rSmapiInfo.usUartBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pSettings->uDStoreSize = TP_ABILITIES_DATA_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pSettings->uIStoreSize = TP_ABILITIES_INST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pSettings->uIps = TP_ABILITIES_INTS_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (pSettings->bDSPEnabled && pSettings->bModemEnabled && pSettings->usDspIrq == pSettings->usUartIrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pBDData->bShareDspIrq = pBDData->bShareUartIrq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pBDData->bShareDspIrq = pBDData->bShareUartIrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_CalcResources exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct resource *pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "tp3780i::tp3780I_ClaimResources entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pres = request_region(pSettings->usDspBaseIO, 16, "mwave_3780i");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if ( pres == NULL ) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_ClaimResources: Error: Could not claim I/O region starting at %x\n", pSettings->usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ClaimResources exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "tp3780i::tp3780I_ReleaseResources entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) release_region(pSettings->usDspBaseIO & (~3), 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (pSettings->bInterruptClaimed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) free_irq(pSettings->usDspIrq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pSettings->bInterruptClaimed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "tp3780i::tp3780I_ReleaseResources exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bool bDSPPoweredUp = false, bInterruptAllocated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (pBDData->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: DSP already enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!pSettings->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780::tp3780I_EnableDSP: Error: pSettings->bDSPEnabled not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (pSettings->usDspIrq >= s_numIrqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) || (pSettings->usDspDma >= s_numDmas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) || (s_ausThinkpadIrqToField[pSettings->usDspIrq] == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) || (s_ausThinkpadDmaToField[pSettings->usDspDma] == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: invalid irq %x\n", pSettings->usDspIrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ((pSettings->usDspBaseIO & 0xF00F) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) || (pSettings->usDspBaseIO & 0x0FF0) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid DSP base I/O address %x\n", pSettings->usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (pSettings->bModemEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pSettings->usUartIrq >= s_numIrqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) || s_ausThinkpadIrqToField[pSettings->usUartIrq] == 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Invalid UART IRQ %x\n", pSettings->usUartIrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (pSettings->usUartBaseIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 0x03F8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case 0x02F8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case 0x03E8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 0x02E8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Invalid UART base I/O address %x\n", pSettings->usUartBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pSettings->bDspIrqActiveLow = pSettings->bDspIrqPulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pSettings->bUartIrqActiveLow = pSettings->bUartIrqPulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pBDData->bShareDspIrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pSettings->bDspIrqActiveLow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (pBDData->bShareUartIrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pSettings->bUartIrqActiveLow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pSettings->usNumTransfers = TP_CFG_NumTransfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pSettings->usReRequest = TP_CFG_RerequestTimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pSettings->bEnableMEMCS16 = TP_CFG_MEMCS16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pSettings->usIsaMemCmdWidth = TP_CFG_IsaMemCmdWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pSettings->bGateIOCHRDY = TP_CFG_GateIOCHRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pSettings->bEnablePwrMgmt = TP_CFG_EnablePwrMgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pSettings->usHBusTimerLoadValue = TP_CFG_HBusTimerValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pSettings->bDisableLBusTimeout = TP_CFG_DisableLBusTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pSettings->usN_Divisor = TP_CFG_N_Divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pSettings->usM_Multiplier = TP_CFG_M_Multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pSettings->bPllBypass = TP_CFG_PllBypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pSettings->usChipletEnable = TP_CFG_ChipletEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (request_irq(pSettings->usUartIrq, &UartInterrupt, 0, "mwave_uart", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Could not get UART IRQ %x\n", pSettings->usUartIrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else { /* no conflict just release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) free_irq(pSettings->usUartIrq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (request_irq(pSettings->usDspIrq, &DspInterrupt, 0, "mwave_3780i", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x\n", pSettings->usDspIrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PRINTK_3(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "tp3780i::tp3780I_EnableDSP, got interrupt %x bShareDspIrq %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pSettings->usDspIrq, pBDData->bShareDspIrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bInterruptAllocated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pSettings->bInterruptClaimed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) smapi_set_DSP_power_state(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (smapi_set_DSP_power_state(true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: smapi_set_DSP_power_state(true) failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bDSPPoweredUp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (dsp3780I_EnableDSP(pSettings, s_ausThinkpadIrqToField, s_ausThinkpadDmaToField)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: dsp7880I_EnableDSP() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) goto exit_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) EnableSRAM(pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pBDData->bDSPEnabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PRINTK_1(TRACE_TP3780I, "tp3780i::tp3780I_EnableDSP exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) exit_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Cleaning up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (bDSPPoweredUp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) smapi_set_DSP_power_state(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (bInterruptAllocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) free_irq(pSettings->usDspIrq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pSettings->bInterruptClaimed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (pBDData->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dsp3780I_DisableDSP(&pBDData->rDspSettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (pSettings->bInterruptClaimed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) free_irq(pSettings->usDspIrq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pSettings->bInterruptClaimed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) smapi_set_DSP_power_state(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pBDData->bDSPEnabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_DisableDSP exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP entry pBDData %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (dsp3780I_Reset(pSettings) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) EnableSRAM(pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ResetDSP exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (dsp3780I_Run(pSettings) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) // @BUG @TBD EnableSRAM(pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_StartDSP exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "tp3780i::tp3780I_QueryAbilities entry pBDData %p\n", pBDData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) memset(pAbilities, 0, sizeof(*pAbilities));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* fill out standard constant fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pAbilities->instr_per_sec = pBDData->rDspSettings.uIps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pAbilities->data_size = pBDData->rDspSettings.uDStoreSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pAbilities->inst_size = pBDData->rDspSettings.uIStoreSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pAbilities->bus_dma_bw = pBDData->rDspSettings.uDmaBandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* fill out dynamically determined fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pAbilities->component_list[0] = 0x00010000 | MW_ADC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pAbilities->component_list[1] = 0x00010000 | MW_ACI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pAbilities->component_list[2] = 0x00010000 | MW_AIC1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pAbilities->component_list[3] = 0x00010000 | MW_AIC2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pAbilities->component_list[4] = 0x00010000 | MW_CDDAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pAbilities->component_list[5] = 0x00010000 | MW_MIDI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pAbilities->component_list[6] = 0x00010000 | MW_UART_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pAbilities->component_count = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Fill out Mwave OS and BIOS task names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) memcpy(pAbilities->mwave_os_name, TP_ABILITIES_MWAVEOS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sizeof(TP_ABILITIES_MWAVEOS_NAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) memcpy(pAbilities->bios_task_name, TP_ABILITIES_BIOSTASK_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sizeof(TP_ABILITIES_BIOSTASK_NAME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PRINTK_1(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "tp3780i::tp3780I_QueryAbilities exit retval=SUCCESSFUL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) void __user *pvBuffer, unsigned int uCount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bool bRC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PRINTK_6(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "tp3780i::tp3780I_ReadWriteDspDStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (pBDData->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (uOpcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case IOCTL_MW_READ_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bRC = dsp3780I_ReadDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case IOCTL_MW_READCLEAR_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bRC = dsp3780I_ReadAndClearDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case IOCTL_MW_WRITE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bRC = dsp3780I_WriteDStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) retval = (bRC) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PRINTK_2(TRACE_TP3780I, "tp3780i::tp3780I_ReadWriteDspDStore exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) void __user *pvBuffer, unsigned int uCount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DSP_3780I_CONFIG_SETTINGS *pSettings = &pBDData->rDspSettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bool bRC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PRINTK_6(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "tp3780i::tp3780I_ReadWriteDspIStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pBDData, uOpcode, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (pBDData->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (uOpcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case IOCTL_MW_READ_INST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bRC = dsp3780I_ReadIStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case IOCTL_MW_WRITE_INST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bRC = dsp3780I_WriteIStore(usDspBaseIO, pvBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) retval = (bRC) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PRINTK_2(TRACE_TP3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "tp3780i::tp3780I_ReadWriteDspIStore exit retval %x\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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