Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) * 3780i.h -- declarations for 3780i.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) * Written By: Mike Sullivan IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) * Copyright (C) 1999 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) * solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) * distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) * exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) * the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) * programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) * DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) * 10/23/2000 - Alpha Release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) *	First release to the public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #ifndef _LINUX_3780I_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define _LINUX_3780I_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* DSP I/O port offsets and definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DSP_IsaSlaveControl        0x0000	/* ISA slave control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DSP_IsaSlaveStatus         0x0001	/* ISA slave status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DSP_ConfigAddress          0x0002	/* General config address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DSP_ConfigData             0x0003	/* General config data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DSP_HBridgeControl         0x0002	/* HBridge control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DSP_MsaAddrLow             0x0004	/* MSP System Address, low word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DSP_MsaAddrHigh            0x0006	/* MSP System Address, high word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DSP_MsaDataDSISHigh        0x0008	/* MSA data register: d-store word or high byte of i-store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DSP_MsaDataISLow           0x000A	/* MSA data register: low word of i-store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DSP_ReadAndClear           0x000C	/* MSA read and clear data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DSP_Interrupt              0x000E	/* Interrupt register (IPC source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned char ClockControl:1;	/* RW: Clock control: 0=normal, 1=stop 3780i clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned char SoftReset:1;	/* RW: Soft reset 0=normal, 1=soft reset active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned char ConfigMode:1;	/* RW: Configuration mode, 0=normal, 1=config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned short Reserved:13;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) } DSP_ISA_SLAVE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned short EnableDspInt:1;	/* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned short MemAutoInc:1;	/* RW: Memory address auto increment, 0=disable, 1=enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	unsigned short IoAutoInc:1;	/* RW: I/O address auto increment, 0=disable, 1=enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned short DiagnosticMode:1;	/* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned short IsaPacingTimer:12;	/* R: ISA access pacing timer: count of core cycles stolen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) } DSP_HBRIDGE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* DSP register indexes used with the configuration register address (index) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DSP_UartCfg1Index          0x0003	/* UART config register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DSP_UartCfg2Index          0x0004	/* UART config register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DSP_HBridgeCfg1Index       0x0007	/* HBridge config register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DSP_HBridgeCfg2Index       0x0008	/* HBridge config register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DSP_BusMasterCfg1Index     0x0009	/* ISA bus master config register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DSP_BusMasterCfg2Index     0x000A	/* ISA bus master config register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DSP_IsaProtCfgIndex        0x000F	/* ISA protocol control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DSP_PowerMgCfgIndex        0x0010	/* Low poser suspend/resume enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DSP_HBusTimerCfgIndex      0x0011	/* HBUS timer load value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned char IrqActiveLow:1;	/* RW: IRQ active high or low: 0=high, 1=low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned char IrqPulse:1;	/* RW: IRQ pulse or level: 0=level, 1=pulse  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned char Irq:3;	/* RW: IRQ selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned char BaseIO:2;	/* RW: Base I/O selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned char Reserved:1;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } DSP_UART_CFG_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned char Enable:1;	/* RW: Enable I/O and IRQ: 0=false, 1=true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned char Reserved:7;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } DSP_UART_CFG_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned char IrqActiveLow:1;	/* RW: IRQ active high=0 or low=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned char IrqPulse:1;	/* RW: IRQ pulse=1 or level=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned char Irq:3;	/* RW: IRQ selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned char AccessMode:1;	/* RW: 16-bit register access method 0=byte, 1=word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned char Reserved:2;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } DSP_HBRIDGE_CFG_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned char Enable:1;	/* RW: enable I/O and IRQ: 0=false, 1=true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned char Reserved:7;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } DSP_HBRIDGE_CFG_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned char Dma:3;	/* RW: DMA channel selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned char NumTransfers:2;	/* RW: Maximum # of transfers once being granted the ISA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned char ReRequest:2;	/* RW: Minimum delay between releasing the ISA bus and requesting it again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned char MEMCS16:1;	/* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } DSP_BUSMASTER_CFG_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned char IsaMemCmdWidth:2;	/* RW: ISA memory command width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned char Reserved:6;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } DSP_BUSMASTER_CFG_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned char GateIOCHRDY:1;	/* RW: Enable IOCHRDY gating: 0=false, 1=true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned char Reserved:7;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } DSP_ISA_PROT_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned char Enable:1;	/* RW: Enable low power suspend/resume 0=false, 1=true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned char Reserved:7;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } DSP_POWER_MGMT_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned char LoadValue:8;	/* RW: HBUS timer load value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } DSP_HBUS_TIMER_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* DSP registers that exist in MSA I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DSP_ChipID                 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DSP_MspBootDomain          0x80000580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DSP_LBusTimeoutDisable     0x80000580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DSP_ClockControl_1         0x8000058A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DSP_ClockControl_2         0x8000058C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DSP_ChipReset              0x80000588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DSP_GpioModeControl_15_8   0x80000082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DSP_GpioDriverEnable_15_8  0x80000076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DSP_GpioOutputData_15_8    0x80000072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned short NMI:1;	/* RW: non maskable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned short Halt:1;	/* RW: Halt MSP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned short ResetCore:1;	/* RW: Reset MSP core interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned short Reserved:13;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } DSP_BOOT_DOMAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned short DisableTimeout:1;	/* RW: Disable LBus timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned short Reserved:15;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } DSP_LBUS_TIMEOUT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned short Memory:1;	/* RW: Reset memory interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned short SerialPort1:1;	/* RW: Reset serial port 1 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned short SerialPort2:1;	/* RW: Reset serial port 2 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned short SerialPort3:1;	/* RW: Reset serial port 3 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned short Gpio:1;	/* RW: Reset GPIO interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned short Dma:1;	/* RW: Reset DMA interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned short SoundBlaster:1;	/* RW: Reset soundblaster interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned short Uart:1;	/* RW: Reset UART interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned short Midi:1;	/* RW: Reset MIDI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned short IsaMaster:1;	/* RW: Reset ISA master interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned short Reserved:6;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } DSP_CHIP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned short N_Divisor:6;	/* RW: (N) PLL output clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned short Reserved1:2;	/* 0: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned short M_Multiplier:6;	/* RW: (M) PLL feedback clock multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	unsigned short Reserved2:2;	/* 0: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } DSP_CLOCK_CONTROL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned short PllBypass:1;	/* RW: PLL Bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned short Reserved:15;	/* 0: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } DSP_CLOCK_CONTROL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned short Latch8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	unsigned short Latch9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	unsigned short Latch10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned short Latch11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	unsigned short Latch12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned short Latch13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned short Latch14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned short Latch15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned short Mask8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	unsigned short Mask9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned short Mask10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned short Mask11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned short Mask12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned short Mask13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned short Mask14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned short Mask15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } DSP_GPIO_OUTPUT_DATA_15_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned short Enable8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned short Enable9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned short Enable10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned short Enable11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned short Enable12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned short Enable13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	unsigned short Enable14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	unsigned short Enable15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unsigned short Mask8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned short Mask9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	unsigned short Mask10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	unsigned short Mask11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	unsigned short Mask12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned short Mask13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	unsigned short Mask14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	unsigned short Mask15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } DSP_GPIO_DRIVER_ENABLE_15_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned short GpioMode8:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	unsigned short GpioMode9:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned short GpioMode10:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned short GpioMode11:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned short GpioMode12:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned short GpioMode13:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned short GpioMode14:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned short GpioMode15:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } DSP_GPIO_MODE_15_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Component masks that are defined in dspmgr.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MW_ADC_MASK    0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MW_AIC2_MASK   0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MW_MIDI_MASK   0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MW_CDDAC_MASK  0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MW_AIC1_MASK   0xE006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MW_UART_MASK   0xE00A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MW_ACI_MASK    0xE00B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Definition of 3780i configuration structure.  Unless otherwise stated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * these values are provided as input to the 3780i support layer.  At present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * the only values maintained by the 3780i support layer are the saved UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) typedef struct _DSP_3780I_CONFIG_SETTINGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* Location of base configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	unsigned short usBaseConfigIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* Enables for various DSP components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int bDSPEnabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int bModemEnabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int bInterruptClaimed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* IRQ, DMA, and Base I/O addresses for various DSP components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	unsigned short usDspIrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	unsigned short usDspDma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned short usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	unsigned short usUartIrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned short usUartBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* IRQ modes for various DSP components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int bDspIrqActiveLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	int bUartIrqActiveLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int bDspIrqPulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int bUartIrqPulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Card abilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	unsigned uIps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	unsigned uDStoreSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	unsigned uIStoreSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	unsigned uDmaBandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Adapter specific 3780i settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	unsigned short usNumTransfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	unsigned short usReRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int bEnableMEMCS16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	unsigned short usIsaMemCmdWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int bGateIOCHRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int bEnablePwrMgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned short usHBusTimerLoadValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	int bDisableLBusTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	unsigned short usN_Divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	unsigned short usM_Multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int bPllBypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	unsigned short usChipletEnable;	/* Used with the chip reset register to enable specific chiplets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* Saved UART registers. These are maintained by the 3780i support layer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int bUartSaved;		/* True after a successful save of the UART registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	unsigned char ucIER;	/* Interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	unsigned char ucFCR;	/* FIFO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	unsigned char ucLCR;	/* Line control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	unsigned char ucMCR;	/* Modem control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	unsigned char ucSCR;	/* Scratch register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unsigned char ucDLL;	/* Divisor latch, low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	unsigned char ucDLM;	/* Divisor latch, high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } DSP_3780I_CONFIG_SETTINGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* 3780i support functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)                        unsigned short *pIrqMap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)                        unsigned short *pDmaMap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)                         unsigned uCount, unsigned long ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)                                 void __user *pvBuffer, unsigned uCount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)                                 unsigned long ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)                          unsigned uCount, unsigned long ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)                         unsigned uCount, unsigned long ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)                          unsigned uCount, unsigned long ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)                                    unsigned long ulMsaAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)                           unsigned long ulMsaAddr, unsigned short usValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)                           unsigned short *pusIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* I/O port access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MKWORD(var) (*((unsigned short *)(&var)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MKBYTE(var) (*((unsigned char *)(&var)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define WriteMsaCfg(addr,value) dsp3780I_WriteMsaCfg(usDspBaseIO,addr,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ReadMsaCfg(addr) dsp3780I_ReadMsaCfg(usDspBaseIO,addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define WriteGenCfg(index,value) dsp3780I_WriteGenCfg(usDspBaseIO,index,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ReadGenCfg(index) dsp3780I_ReadGenCfg(usDspBaseIO,index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define InWordDsp(index)          inw(usDspBaseIO+index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define InByteDsp(index)          inb(usDspBaseIO+index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OutWordDsp(index,value)   outw(value,usDspBaseIO+index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OutByteDsp(index,value)   outb(value,usDspBaseIO+index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif