^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 3780i.c -- helper routines for the 3780i DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written By: Mike Sullivan IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 10/23/2000 - Alpha Release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * First release to the public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/sched.h> /* cond_resched() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "smapi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "mwavedd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "3780i.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static DEFINE_SPINLOCK(dsp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void PaceMsaAccess(unsigned short usDspBaseIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long ulMsaAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usDspBaseIO, ulMsaAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = InWordDsp(DSP_MsaDataDSISHigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long ulMsaAddr, unsigned short usValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PRINTK_4(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) usDspBaseIO, ulMsaAddr, usValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) OutWordDsp(DSP_MsaDataDSISHigh, usValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned char ucValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DSP_ISA_SLAVE_CONTROL rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PRINTK_4(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) usDspBaseIO, uIndex, ucValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MKBYTE(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rSlaveControl_Save = rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rSlaveControl.ConfigMode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MKBYTE(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OutByteDsp(DSP_ConfigData, ucValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned uIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DSP_ISA_SLAVE_CONTROL rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned char ucValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) usDspBaseIO, uIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rSlaveControl_Save = rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rSlaveControl.ConfigMode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ucValue = InByteDsp(DSP_ConfigData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ucValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned short *pIrqMap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned short *pDmaMap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DSP_UART_CFG_1 rUartCfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DSP_UART_CFG_2 rUartCfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DSP_ISA_PROT_CFG rIsaProtCfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DSP_POWER_MGMT_CFG rPowerMgmtCfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DSP_HBUS_TIMER_CFG rHBusTimerCfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DSP_CHIP_RESET rChipReset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DSP_CLOCK_CONTROL_1 rClockControl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DSP_CLOCK_CONTROL_2 rClockControl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DSP_ISA_SLAVE_CONTROL rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DSP_HBRIDGE_CONTROL rHBridgeControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned short ChipID = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned short tval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pSettings->bDSPEnabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!pSettings->bDSPEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pSettings->bModemEnabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (pSettings->bModemEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rUartCfg1.Irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (unsigned char) pIrqMap[pSettings->usUartIrq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (pSettings->usUartBaseIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case 0x03F8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rUartCfg1.BaseIO = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case 0x02F8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rUartCfg1.BaseIO = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case 0x03E8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rUartCfg1.BaseIO = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case 0x02E8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rUartCfg1.BaseIO = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rUartCfg2.Enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rHBridgeCfg1.AccessMode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rHBridgeCfg2.Enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rBusmasterCfg2.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rBusmasterCfg1.NumTransfers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (unsigned char) pSettings->usNumTransfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rBusmasterCfg2.IsaMemCmdWidth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (unsigned char) pSettings->usIsaMemCmdWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rIsaProtCfg.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rPowerMgmtCfg.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rHBusTimerCfg.LoadValue =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (unsigned char) pSettings->usHBusTimerLoadValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rLBusTimeoutDisable.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rLBusTimeoutDisable.DisableTimeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pSettings->bDisableLBusTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MKWORD(rChipReset) = ~pSettings->usChipletEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rClockControl1.N_Divisor = pSettings->usN_Divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rClockControl2.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rClockControl2.PllBypass = pSettings->bPllBypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Issue a soft reset to the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * soft-reset active for 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rSlaveControl.ClockControl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rSlaveControl.SoftReset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rSlaveControl.ConfigMode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rSlaveControl.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PRINTK_4(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) usDspBaseIO, DSP_IsaSlaveControl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) usDspBaseIO + DSP_IsaSlaveControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MKWORD(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < 11; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) udelay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) rSlaveControl.SoftReset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Program our general configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (pSettings->bModemEnabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rHBridgeControl.EnableDspInt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rHBridgeControl.MemAutoInc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) rHBridgeControl.IoAutoInc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) rHBridgeControl.DiagnosticMode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ChipID = ReadMsaCfg(DSP_ChipID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "3780i::dsp3780I_EnableDSP exiting bRC=true, ChipID %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ChipID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DSP_ISA_SLAVE_CONTROL rSlaveControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rSlaveControl.ClockControl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rSlaveControl.SoftReset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rSlaveControl.ConfigMode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rSlaveControl.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rSlaveControl.ClockControl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DSP_BOOT_DOMAIN rBootDomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DSP_HBRIDGE_CONTROL rHBridgeControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Mask DSP to PC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rHBridgeControl.EnableDspInt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Reset the core via the boot domain register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rBootDomain.ResetCore = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rBootDomain.Halt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rBootDomain.NMI = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rBootDomain.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MKWORD(rBootDomain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Reset all the chiplets and then reactivate them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) WriteMsaCfg(DSP_ChipReset, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) WriteMsaCfg(DSP_ChipReset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (unsigned short) (~pSettings->usChipletEnable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned short usDspBaseIO = pSettings->usDspBaseIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DSP_BOOT_DOMAIN rBootDomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DSP_HBRIDGE_CONTROL rHBridgeControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Transition the core to a running state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rBootDomain.ResetCore = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rBootDomain.Halt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rBootDomain.NMI = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rBootDomain.Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rBootDomain.ResetCore = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rBootDomain.NMI = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Enable DSP to PC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) rHBridgeControl.EnableDspInt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned uCount, unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned short __user *pusBuffer = pvBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PRINTK_5(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Set the initial MSA address. No adjustments need to be made to data store addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Transfer the memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) while (uCount-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val = InWordDsp(DSP_MsaDataDSISHigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if(put_user(val, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uCount, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PaceMsaAccess(usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PRINTK_1(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "3780I::dsp3780I_ReadDStore exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) void __user *pvBuffer, unsigned uCount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned short __user *pusBuffer = pvBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PRINTK_5(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Set the initial MSA address. No adjustments need to be made to data store addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Transfer the memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) while (uCount-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val = InWordDsp(DSP_ReadAndClear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if(put_user(val, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uCount, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PaceMsaAccess(usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PRINTK_1(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "3780I::dsp3780I_ReadAndClearDStore exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned uCount, unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned short __user *pusBuffer = pvBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PRINTK_5(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Set the initial MSA address. No adjustments need to be made to data store addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Transfer the memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) while (uCount-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if(get_user(val, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OutWordDsp(DSP_MsaDataDSISHigh, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uCount, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PaceMsaAccess(usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PRINTK_1(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "3780I::dsp3780D_WriteDStore exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned uCount, unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned short __user *pusBuffer = pvBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PRINTK_5(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Set the initial MSA address. To convert from an instruction store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * address to an MSA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * shift the address two bits to the left and set bit 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Transfer the memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) while (uCount-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned short val_lo, val_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val_lo = InWordDsp(DSP_MsaDataISLow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val_hi = InWordDsp(DSP_MsaDataDSISHigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if(put_user(val_lo, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if(put_user(val_hi, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PRINTK_4(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) uCount, val_lo, val_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PaceMsaAccess(usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PRINTK_1(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "3780I::dsp3780I_ReadIStore exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned uCount, unsigned long ulDSPAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned short __user *pusBuffer = pvBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PRINTK_5(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Set the initial MSA address. To convert from an instruction store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * address to an MSA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * shift the address two bits to the left and set bit 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Transfer the memory block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) while (uCount-- != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned short val_lo, val_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if(get_user(val_lo, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if(get_user(val_hi, pusBuffer++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) OutWordDsp(DSP_MsaDataISLow, val_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PRINTK_4(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) uCount, val_lo, val_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PaceMsaAccess(usDspBaseIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PRINTK_1(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "3780I::dsp3780I_WriteIStore exit bRC=true\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned short *pusIPCSource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) DSP_HBRIDGE_CONTROL rHBridgeControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned short temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) usDspBaseIO, pusIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * Disable DSP to PC interrupts, read the interrupt register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * clear the pending IPC bits, and reenable DSP to PC interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) spin_lock_irqsave(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rHBridgeControl.EnableDspInt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *pusIPCSource = InWordDsp(DSP_Interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) temp = (unsigned short) ~(*pusIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PRINTK_3(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) *pusIPCSource, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rHBridgeControl.EnableDspInt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_unlock_irqrestore(&dsp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PRINTK_2(TRACE_3780I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *pusIPCSource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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