Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * A hack to create a platform device from a DMI entry.  This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * allow autoloading of the IPMI drive based on SMBIOS entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define pr_fmt(fmt) "%s" fmt, "ipmi:dmi: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define dev_fmt pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/ipmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ipmi_dmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "ipmi_plat_data.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IPMI_DMI_TYPE_KCS	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IPMI_DMI_TYPE_SMIC	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IPMI_DMI_TYPE_BT	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IPMI_DMI_TYPE_SSIF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct ipmi_dmi_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	enum si_type si_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int space; /* addr space for si, intf# for ssif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u8 slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct ipmi_dmi_info *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static struct ipmi_dmi_info *ipmi_dmi_infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int ipmi_dmi_nr __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static void __init dmi_add_platform_ipmi(unsigned long base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 					 unsigned int space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 					 u8 slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 					 int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 					 int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 					 int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct ipmi_dmi_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct ipmi_plat_data p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	memset(&p, 0, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	name = "dmi-ipmi-si";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	p.iftype = IPMI_PLAT_IF_SI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	case IPMI_DMI_TYPE_SSIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		name = "dmi-ipmi-ssif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		p.iftype = IPMI_PLAT_IF_SSIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		p.type = SI_TYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	case IPMI_DMI_TYPE_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		p.type = SI_BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case IPMI_DMI_TYPE_KCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		p.type = SI_KCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case IPMI_DMI_TYPE_SMIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		p.type = SI_SMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		pr_err("Invalid IPMI type: %d\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	p.addr = base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	p.space = space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	p.regspacing = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	p.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	p.slave_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	p.addr_source = SI_SMBIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	info = kmalloc(sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		pr_warn("Could not allocate dmi info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		info->si_type = p.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		info->space = space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		info->addr = base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		info->slave_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		info->next = ipmi_dmi_infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		ipmi_dmi_infos = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (ipmi_platform_add(name, ipmi_dmi_nr, &p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		ipmi_dmi_nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Look up the slave address for a given interface.  This is here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * because ACPI doesn't have a slave address while SMBIOS does, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * prefer using ACPI so the ACPI code can use the IPMI namespace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * This function allows an ACPI-specified IPMI device to look up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * slave address from the DMI table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ipmi_dmi_get_slave_addr(enum si_type si_type, unsigned int space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			    unsigned long base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct ipmi_dmi_info *info = ipmi_dmi_infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	while (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (info->si_type == si_type &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		    info->space == space &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		    info->addr == base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			return info->slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		info = info->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXPORT_SYMBOL(ipmi_dmi_get_slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DMI_IPMI_MIN_LENGTH	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DMI_IPMI_VER2_LENGTH	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DMI_IPMI_TYPE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DMI_IPMI_SLAVEADDR	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMI_IPMI_ADDR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMI_IPMI_ACCESS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DMI_IPMI_IRQ		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DMI_IPMI_IO_MASK	0xfffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void __init dmi_decode_ipmi(const struct dmi_header *dm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	const u8 *data = (const u8 *) dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int space = IPMI_IO_ADDR_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u8 len = dm->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int irq = 0, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (len < DMI_IPMI_MIN_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	type = data[DMI_IPMI_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	slave_addr = data[DMI_IPMI_SLAVEADDR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	memcpy(&base_addr, data + DMI_IPMI_ADDR, sizeof(unsigned long));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (!base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		pr_err("Base address is zero, assuming no IPMI interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (len >= DMI_IPMI_VER2_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (type == IPMI_DMI_TYPE_SSIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			space = 0; /* Match I2C interface 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			base_addr = data[DMI_IPMI_ADDR] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			if (base_addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 * Some broken systems put the I2C address in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				 * the slave address field.  We try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				 * accommodate them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				base_addr = data[DMI_IPMI_SLAVEADDR] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				slave_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			if (base_addr & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				/* I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				base_addr &= DMI_IPMI_IO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				/* Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				space = IPMI_MEM_ADDR_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			 * If bit 4 of byte 0x10 is set, then the lsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			 * for the address is odd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			base_addr |= (data[DMI_IPMI_ACCESS] >> 4) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			irq = data[DMI_IPMI_IRQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			 * The top two bits of byte 0x10 hold the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			 * register spacing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			switch ((data[DMI_IPMI_ACCESS] >> 6) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			case 0: /* Byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			case 1: /* 32-bit boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				offset = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			case 2: /* 16-byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				pr_err("Invalid offset: 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* Old DMI spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 * Note that technically, the lower bit of the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 * address should be 1 if the address is I/O and 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		 * the address is in memory.  So many systems get that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		 * wrong (and all that I have seen are I/O) so we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		 * ignore that bit and assume I/O.  Systems that use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		 * memory should use the newer spec, anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		base_addr = base_addr & DMI_IPMI_IO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dmi_add_platform_ipmi(base_addr, space, slave_addr, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			      offset, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init scan_for_dmi_ipmi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	const struct dmi_device *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	while ((dev = dmi_find_device(DMI_DEV_TYPE_IPMI, NULL, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dmi_decode_ipmi((const struct dmi_header *) dev->device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) subsys_initcall(scan_for_dmi_ipmi);