^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2020 Xiphera Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CONTROL_REG 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STATUS_REG 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RAND_REG 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HOST_TO_TRNG_RESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HOST_TO_TRNG_RELEASE_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HOST_TO_TRNG_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HOST_TO_TRNG_ZEROIZE 0x80000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HOST_TO_TRNG_ACK_ZEROIZE 0x80000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HOST_TO_TRNG_READ 0x8000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* trng statuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TRNG_ACK_RESET 0x000000AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TRNG_SUCCESSFUL_STARTUP 0x00000057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TRNG_FAILED_STARTUP 0x000000FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TRNG_NEW_RAND_AVAILABLE 0x000000ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct xiphera_trng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int xiphera_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct xiphera_trng *trng = container_of(rng, struct xiphera_trng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) while (max >= sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* check for data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *(u32 *)buf = readl(trng->mem + RAND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Inform the trng of the read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * and re-enable it to produce a new random number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) buf += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) max -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int xiphera_trng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct xiphera_trng *trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) trng = devm_kzalloc(dev, sizeof(*trng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) trng->mem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (IS_ERR(trng->mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return PTR_ERR(trng->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * the trng needs to be reset first which might not happen in time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * hence we incorporate a small delay to ensure proper behaviour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * there is a small chance the trng is just not ready yet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * so we try one more time. If the second time fails, we give up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(dev, "failed to reset the trng ip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * once again, to ensure proper behaviour we sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * for a while after zeroizing the trng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (readl(trng->mem + STATUS_REG) != TRNG_SUCCESSFUL_STARTUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* diagnose the reason for the failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (readl(trng->mem + STATUS_REG) == TRNG_FAILED_STARTUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dev, "trng ip startup-tests failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(dev, "startup-tests yielded no response\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) trng->rng.name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) trng->rng.read = xiphera_trng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) trng->rng.quality = 900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = devm_hwrng_register(dev, &trng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(dev, "failed to register rng device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) platform_set_drvdata(pdev, trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct of_device_id xiphera_trng_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .compatible = "xiphera,xip8001b-trng", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MODULE_DEVICE_TABLE(of, xiphera_trng_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct platform_driver xiphera_trng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "xiphera-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .of_match_table = xiphera_trng_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .probe = xiphera_trng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) module_platform_driver(xiphera_trng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_AUTHOR("Atte Tommiska");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_DESCRIPTION("Xiphera FPGA-based true random number generator driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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