Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * APM X-Gene SoC RNG Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	   Shamal Winchurkar <swinchurkar@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	   Feng Kan <fkan@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RNG_MAX_DATUM			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX_TRY				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define XGENE_RNG_RETRY_COUNT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define XGENE_RNG_RETRY_INTERVAL	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* RNG  Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RNG_INOUT_0			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RNG_INTR_STS_ACK		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RNG_CONTROL			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RNG_CONFIG			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RNG_ALARMCNT			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RNG_FROENABLE			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RNG_FRODETUNE			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RNG_ALARMMASK			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RNG_ALARMSTOP			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RNG_OPTIONS			0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RNG_EIP_REV			0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MONOBIT_FAIL_MASK		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define POKER_FAIL_MASK			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LONG_RUN_FAIL_MASK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RUN_FAIL_MASK			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define NOISE_FAIL_MASK			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define STUCK_OUT_MASK			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SHUTDOWN_OFLO_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define READY_MASK			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAJOR_HW_REV_RD(src)		(((src) & 0x0f000000) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MINOR_HW_REV_RD(src)		(((src) & 0x00f00000) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HW_PATCH_LEVEL_RD(src)		(((src) & 0x000f0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX_REFILL_CYCLES_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MIN_REFILL_CYCLES_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ALARM_THRESHOLD_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ENABLE_RNG_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REGSPEC_TEST_MODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MONOBIT_FAIL_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define POKER_FAIL_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define LONG_RUN_FAIL_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RUN_FAIL_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define NOISE_FAIL_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define STUCK_OUT_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct xgene_rng_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	void  __iomem *csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 datum_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 failure_cnt;	/* Failure count last minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned long failure_ts;/* First failure timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct timer_list failure_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void xgene_rng_expired_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Clear failure counter as timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	disable_irq(ctx->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ctx->failure_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	del_timer(&ctx->failure_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	enable_irq(ctx->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ctx->failure_timer.expires = jiffies + 120 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	add_timer(&ctx->failure_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * Initialize or reinit free running oscillators (FROs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (val & MONOBIT_FAIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		 * LFSR detected an out-of-bounds number of 1s after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		 * checking 20,000 bits (test T1 as specified in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		 * AIS-31 standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (val & POKER_FAIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		 * LFSR detected an out-of-bounds value in at least one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		 * of the 16 poker_count_X counters or an out of bounds sum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 * of squares value after checking 20,000 bits (test T2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 * specified in the AIS-31 standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (val & LONG_RUN_FAIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * LFSR detected a sequence of 34 identical bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * (test T4 as specified in the AIS-31 standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (val & RUN_FAIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		 * LFSR detected an outof-bounds value for at least one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		 * of the running counters after checking 20,000 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		 * (test T3 as specified in the AIS-31 standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (val & NOISE_FAIL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* LFSR detected a sequence of 48 identical bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (val & STUCK_OUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 * Detected output data registers generated same value twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 * in a row
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (val & SHUTDOWN_OFLO_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		u32 frostopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		/* FROs shut down after a second error event. Try recover. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (++ctx->failure_cnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			/* 1st time, just recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			ctx->failure_ts = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			xgene_rng_init_fro(ctx, frostopped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			 * We must start a timer to clear out this error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			 * in case the system timer wrap around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			xgene_rng_start_timer(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			/* 2nd time failure in lesser than 1 minute? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					"FRO shutdown failure error 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				/* 2nd time failure after 1 minutes, recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				ctx->failure_ts = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				ctx->failure_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				 * We must start a timer to clear out this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				 * error in case the system timer wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				 * around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				xgene_rng_start_timer(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			xgene_rng_init_fro(ctx, frostopped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Clear them all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* RNG Alarm Counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	xgene_rng_chk_overflow(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int xgene_rng_data_present(struct hwrng *rng, int wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 i, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if ((val & READY_MASK) || !wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		udelay(XGENE_RNG_RETRY_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return (val & READY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	for (i = 0; i < ctx->datum_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Clear ready bit to start next transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return ctx->datum_size << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	writel(0x00000000, ctx->csr_base + RNG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	val = MAX_REFILL_CYCLES_SET(0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	val = MIN_REFILL_CYCLES_SET(val, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel(val, ctx->csr_base + RNG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	val = ALARM_THRESHOLD_SET(0, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel(val, ctx->csr_base + RNG_ALARMCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	xgene_rng_init_fro(ctx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	writel(MONOBIT_FAIL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		POKER_FAIL_MASK	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		LONG_RUN_FAIL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		RUN_FAIL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		NOISE_FAIL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		STUCK_OUT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		SHUTDOWN_OFLO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	val = ENABLE_RNG_SET(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	val = MONOBIT_FAIL_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	val = POKER_FAIL_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	val = LONG_RUN_FAIL_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	val = RUN_FAIL_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	val = NOISE_FAIL_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	val = STUCK_OUT_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	val = SHUTDOWN_OFLO_MASK_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	writel(val, ctx->csr_base + RNG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int xgene_rng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ctx->failure_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		MAJOR_HW_REV_RD(ctx->revision),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		MINOR_HW_REV_RD(ctx->revision),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		HW_PATCH_LEVEL_RD(ctx->revision));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dev_dbg(ctx->dev, "Options 0x%08X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		readl(ctx->csr_base + RNG_OPTIONS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	xgene_rng_init_internal(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ctx->datum_size = RNG_MAX_DATUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct acpi_device_id xgene_rng_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ "APMC0D18", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct hwrng xgene_rng_func = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.name		= "xgene-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.init		= xgene_rng_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.data_present	= xgene_rng_data_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.data_read	= xgene_rng_data_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int xgene_rng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct xgene_rng_dev *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ctx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (IS_ERR(ctx->csr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(ctx->csr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	rc = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ctx->irq = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		ctx->csr_base, ctx->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				dev_name(&pdev->dev), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* Enable IP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ctx->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (IS_ERR(ctx->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		rc = clk_prepare_enable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				 "clock prepare enable failed for RNG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	xgene_rng_func.priv = (unsigned long) ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(&pdev->dev, "RNG registering failed error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		if (!IS_ERR(ctx->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	rc = device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		if (!IS_ERR(ctx->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int xgene_rng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct xgene_rng_dev *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	rc = device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (!IS_ERR(ctx->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct of_device_id xgene_rng_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ .compatible = "apm,xgene-rng" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_driver xgene_rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.probe = xgene_rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.remove	= xgene_rng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.name		= "xgene-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.of_match_table = xgene_rng_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) module_platform_driver(xgene_rng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_DESCRIPTION("APM X-Gene RNG driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_LICENSE("GPL");