^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, Daniel Thompson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RNG_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RNG_CR_RNGEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RNG_CR_CED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RNG_SR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RNG_SR_SEIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RNG_SR_CEIS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RNG_SR_DRDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RNG_DR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct stm32_rng_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct stm32_rng_private *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) container_of(rng, struct stm32_rng_private, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pm_runtime_get_sync((struct device *) priv->rng.priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) while (max > sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) sr = readl_relaxed(priv->base + RNG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Manage timeout which is based on timer and take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* care of initial delay time when enabling rng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!sr && wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) retval = readl_relaxed_poll_timeout_atomic(priv->base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) + RNG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sr, sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 10, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err((struct device *)priv->rng.priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "%s: timeout %x!\n", __func__, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* If error detected or data not ready... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (sr != RNG_SR_DRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (WARN_ONCE(sr & (RNG_SR_SEIS | RNG_SR_CEIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "bad RNG status - %x\n", sr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(0, priv->base + RNG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *(u32 *)data = readl_relaxed(priv->base + RNG_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) retval += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) data += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) max -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pm_runtime_mark_last_busy((struct device *) priv->rng.priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pm_runtime_put_sync_autosuspend((struct device *) priv->rng.priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return retval || !wait ? retval : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int stm32_rng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct stm32_rng_private *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) container_of(rng, struct stm32_rng_private, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (priv->ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) priv->base + RNG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* clear error indicators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(0, priv->base + RNG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void stm32_rng_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct stm32_rng_private *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) container_of(rng, struct stm32_rng_private, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(0, priv->base + RNG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int stm32_rng_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct stm32_rng_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) err = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) priv->base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) priv->clk = devm_clk_get(&ofdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) priv->rst = devm_reset_control_get(&ofdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!IS_ERR(priv->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) priv->ced = of_property_read_bool(np, "clock-error-detect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) priv->rng.name = dev_driver_string(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifndef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) priv->rng.init = stm32_rng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) priv->rng.cleanup = stm32_rng_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->rng.read = stm32_rng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->rng.priv = (unsigned long) dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) priv->rng.quality = 900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pm_runtime_set_autosuspend_delay(dev, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return devm_hwrng_register(dev, &priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int stm32_rng_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pm_runtime_disable(&ofdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int stm32_rng_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct stm32_rng_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) stm32_rng_cleanup(&priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int stm32_rng_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct stm32_rng_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return stm32_rng_init(&priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct dev_pm_ops stm32_rng_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) stm32_rng_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct of_device_id stm32_rng_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .compatible = "st,stm32-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_DEVICE_TABLE(of, stm32_rng_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct platform_driver stm32_rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "stm32-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pm = &stm32_rng_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .of_match_table = stm32_rng_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .probe = stm32_rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .remove = stm32_rng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) module_platform_driver(stm32_rng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_AUTHOR("Daniel Thompson <daniel.thompson@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_DESCRIPTION("STMicroelectronics STM32 RNG device driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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