^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rockchip-rng.c Random Number Generator driver for the Rockchip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Lin Jinhan <troy.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _SBF(s, v) ((v) << (s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ROCKCHIP_AUTOSUSPEND_DELAY 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ROCKCHIP_POLL_PERIOD_US 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ROCKCHIP_POLL_TIMEOUT_US 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RK_MAX_RNG_BYTE (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* start of CRYPTO V1 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRYPTO_V1_CTRL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRYPTO_V1_RNG_START BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRYPTO_V1_RNG_FLUSH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRYPTO_V1_TRNG_CTRL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRYPTO_V1_OSC_ENABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CRYPTO_V1_TRNG_DOUT_0 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* end of CRYPTO V1 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* start of CRYPTO V2 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CRYPTO_V2_RNG_CTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CRYPTO_V2_RNG_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CRYPTO_V2_RNG_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CRYPTO_V2_RNG_DOUT_0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* end of CRYPTO V2 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* start of TRNG_V1 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* TRNG is no longer subordinate to the Crypto module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TRNG_V1_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TRNG_V1_CTRL_NOP _SBF(0, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TRNG_V1_CTRL_RAND _SBF(0, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TRNG_V1_CTRL_SEED _SBF(0, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TRNG_V1_STAT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TRNG_V1_STAT_SEEDED BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TRNG_V1_STAT_GENERATING BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TRNG_V1_STAT_RESEEDING BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TRNG_V1_MODE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TRNG_V1_MODE_128_BIT _SBF(3, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TRNG_V1_MODE_256_BIT _SBF(3, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TRNG_V1_IE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TRNG_V1_IE_GLBL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TRNG_V1_IE_SEED_DONE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TRNG_V1_IE_RAND_RDY_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TRNG_V1_ISTAT 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TRNG_V1_ISTAT_RAND_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* RAND0 ~ RAND7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TRNG_V1_RAND0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TRNG_V1_RAND7 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TRNG_V1_AUTO_RQSTS 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TRNG_V1_VERSION 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TRNG_v1_VERSION_CODE 0x46bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* end of TRNG_V1 register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rk_rng_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 default_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*rk_rng_init)(struct hwrng *rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct rk_rng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct rk_rng_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk_bulk_data *clk_bulks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __raw_writel(val, rng->mem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return __raw_readl(rng->mem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int rk_rng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void rk_rng_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int read_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!rk_rng->soc_data->rk_rng_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = pm_runtime_get_sync(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pm_runtime_put_noidle(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while (max > ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) max - ret, wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (read_len < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret += read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pm_runtime_mark_last_busy(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pm_runtime_put_sync_autosuspend(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (i = 0; i < size; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 reg_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* enable osc_ring to get entropy, sample period is set as 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) !(reg_ctrl & CRYPTO_V1_RNG_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ROCKCHIP_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ROCKCHIP_POLL_TIMEOUT_US, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rk_rng, CRYPTO_V1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* close TRNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CRYPTO_V1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 reg_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* enable osc_ring to get entropy, sample period is set as 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg_ctrl |= CRYPTO_V2_RNG_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CRYPTO_V2_RNG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) !(reg_ctrl & CRYPTO_V2_RNG_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ROCKCHIP_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ROCKCHIP_POLL_TIMEOUT_US, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rk_rng, CRYPTO_V2_RNG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* close TRNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int rk_trng_v1_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) uint32_t auto_reseed_cnt = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint32_t reg_ctrl, status, version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = pm_runtime_get_sync(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pm_runtime_put_noidle(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (version != TRNG_v1_VERSION_CODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(rk_rng->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "wrong trng version, expected = %08x, actual = %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) TRNG_V1_VERSION, version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!(status & TRNG_V1_STAT_SEEDED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (status & TRNG_V1_STAT_GENERATING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (status & TRNG_V1_STAT_RESEEDING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uint32_t mask = TRNG_V1_STAT_SEEDED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) TRNG_V1_STAT_GENERATING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TRNG_V1_STAT_RESEEDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* wait for GENERATING and RESEEDING flag to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) read_poll_timeout(rk_rng_readl, reg_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ROCKCHIP_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ROCKCHIP_POLL_TIMEOUT_US, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rk_rng, TRNG_V1_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* clear ISTAT flag because trng may auto reseeding when power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pm_runtime_mark_last_busy(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pm_runtime_put_sync_autosuspend(rk_rng->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 reg_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* clear ISTAT anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* generate 256bit random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Generate2 56 bit random data will cost 1024 clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* wait RAND_RDY triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ROCKCHIP_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ROCKCHIP_POLL_TIMEOUT_US, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rk_rng, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* clear all status flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* close TRNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .default_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .rk_rng_read = rk_crypto_v1_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .rk_rng_read = rk_crypto_v2_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .default_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .rk_rng_init = rk_trng_v1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .rk_rng_read = rk_trng_v1_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct of_device_id rk_rng_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .compatible = "rockchip,cryptov1-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .data = (void *)&rk_crypto_v1_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .compatible = "rockchip,cryptov2-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .data = (void *)&rk_crypto_v2_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .compatible = "rockchip,trngv1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .data = (void *)&rk_trng_v1_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int rk_rng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct rk_rng *rk_rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) resource_size_t map_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(&pdev->dev, "probing...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!rk_rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) match = of_match_node(rk_rng_dt_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rk_rng->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rk_rng->rng.name = "rockchip";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifndef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rk_rng->rng.init = rk_rng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rk_rng->rng.cleanup = rk_rng_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rk_rng->rng.read = rk_rng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rk_rng->rng.quality = 999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(rk_rng->mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return PTR_ERR(rk_rng->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* compatible with crypto v2 module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * With old dtsi configurations, the RNG base was equal to the crypto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * base, so both drivers could not be enabled at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * RNG base = CRYPTO base + RNG offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * With new dtsi configurations, CRYPTO regs is divided into two parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * RNG driver and CRYPTO driver could be enabled at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (map_size > rk_rng->soc_data->default_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rk_rng->mem += rk_rng->soc_data->default_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (rk_rng->clk_num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&pdev->dev, "failed to get clks property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) platform_set_drvdata(pdev, rk_rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ROCKCHIP_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* for some platform need hardware operation when probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (rk_rng->soc_data->rk_rng_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int rk_rng_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct rk_rng *rk_rng = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rk_rng_cleanup(&rk_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int rk_rng_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct rk_rng *rk_rng = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return rk_rng_init(&rk_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct dev_pm_ops rk_rng_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rk_rng_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct platform_driver rk_rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "rockchip-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .pm = &rk_rng_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .of_match_table = rk_rng_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .probe = rk_rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) module_platform_driver(rk_rng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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