^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * omap-rng.c - RNG driver for TI OMAP CPU family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2005 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mostly based on original driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RNG_REG_STATUS_RDY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RNG_REG_INTACK_RDY_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RNG_CONTROL_STARTUP_CYCLES 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RNG_ALARM_THRESHOLD 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RNG_SHUTDOWN_THRESHOLD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RNG_REG_FROENABLE_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RNG_REG_FRODETUNE_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP2_RNG_OUTPUT_SIZE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4_RNG_OUTPUT_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EIP76_RNG_OUTPUT_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * EIP76 RNG takes approx. 700us to produce 16 bytes of output data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * as per testing results. And to account for the lack of udelay()'s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * reliability, we keep the timeout as 1000us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RNG_DATA_FILL_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RNG_OUTPUT_0_REG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RNG_OUTPUT_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RNG_OUTPUT_2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RNG_OUTPUT_3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RNG_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RNG_INTMASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RNG_INTACK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RNG_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RNG_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RNG_ALARMCNT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RNG_FROENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RNG_FRODETUNE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RNG_ALARMMASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RNG_ALARMSTOP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RNG_REV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RNG_SYSCONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const u16 reg_map_omap2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [RNG_OUTPUT_0_REG] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [RNG_STATUS_REG] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [RNG_CONFIG_REG] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [RNG_REV_REG] = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [RNG_SYSCONFIG_REG] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const u16 reg_map_omap4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [RNG_OUTPUT_0_REG] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [RNG_OUTPUT_1_REG] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [RNG_STATUS_REG] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [RNG_INTMASK_REG] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [RNG_INTACK_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [RNG_CONTROL_REG] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [RNG_CONFIG_REG] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [RNG_ALARMCNT_REG] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [RNG_FROENABLE_REG] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [RNG_FRODETUNE_REG] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [RNG_ALARMMASK_REG] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [RNG_ALARMSTOP_REG] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [RNG_REV_REG] = 0x1FE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [RNG_SYSCONFIG_REG] = 0x1FE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const u16 reg_map_eip76[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [RNG_OUTPUT_0_REG] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [RNG_OUTPUT_1_REG] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [RNG_OUTPUT_2_REG] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [RNG_OUTPUT_3_REG] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [RNG_STATUS_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [RNG_INTACK_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [RNG_CONTROL_REG] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [RNG_CONFIG_REG] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [RNG_ALARMCNT_REG] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [RNG_FROENABLE_REG] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [RNG_FRODETUNE_REG] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [RNG_ALARMMASK_REG] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [RNG_ALARMSTOP_REG] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [RNG_REV_REG] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct omap_rng_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * struct omap_rng_pdata - RNG IP block-specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @regs: Pointer to the register offsets structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @data_size: No. of bytes in RNG output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @data_present: Callback to determine if data is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @init: Callback for IP specific initialization sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @cleanup: Callback for IP specific cleanup sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct omap_rng_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 (*data_present)(struct omap_rng_dev *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int (*init)(struct omap_rng_dev *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void (*cleanup)(struct omap_rng_dev *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct omap_rng_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const struct omap_rng_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk *clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return __raw_readl(priv->base + priv->pdata->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __raw_writel(val, priv->base + priv->pdata->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int omap_rng_do_read(struct hwrng *rng, void *data, size_t max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct omap_rng_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int i, present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) priv = (struct omap_rng_dev *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (max < priv->pdata->data_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < RNG_DATA_FILL_TIMEOUT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) present = priv->pdata->data_present(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (present || !wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) priv->pdata->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (priv->pdata->regs[RNG_INTACK_REG])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return priv->pdata->data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int omap_rng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct omap_rng_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) priv = (struct omap_rng_dev *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return priv->pdata->init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void omap_rng_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct omap_rng_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv = (struct omap_rng_dev *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) priv->pdata->cleanup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int omap2_rng_init(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void omap2_rng_cleanup(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct omap_rng_pdata omap2_rng_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .regs = (u16 *)reg_map_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .data_size = OMAP2_RNG_OUTPUT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .data_present = omap2_rng_data_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .init = omap2_rng_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cleanup = omap2_rng_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int eip76_rng_init(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Return if RNG is already running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Number of 512 bit blocks of raw Noise Source output data that must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * be processed by either the Conditioning Function or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * SP 800-90 DRBG ‘BC_DF’ functionality to yield a ‘full entropy’
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * output value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Number of FRO samples that are XOR-ed together into one bit to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * shifted into the main shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) omap_rng_write(priv, RNG_CONFIG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Enable all available FROs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Enable TRNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = RNG_CONTROL_ENABLE_TRNG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) omap_rng_write(priv, RNG_CONTROL_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int omap4_rng_init(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Return if RNG is already running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) omap_rng_write(priv, RNG_CONFIG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) omap_rng_write(priv, RNG_ALARMCNT_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val |= RNG_CONTROL_ENABLE_TRNG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) omap_rng_write(priv, RNG_CONTROL_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void omap4_rng_cleanup(struct omap_rng_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val = omap_rng_read(priv, RNG_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) omap_rng_write(priv, RNG_CONTROL_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct omap_rng_dev *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 fro_detune, fro_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Interrupt raised by a fro shutdown threshold, do the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * 1. Clear the alarm events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * 2. De tune the FROs which are shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 3. Re enable the shutdown FROs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fro_enable = RNG_REG_FROENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct omap_rng_pdata omap4_rng_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .regs = (u16 *)reg_map_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .data_size = OMAP4_RNG_OUTPUT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .data_present = omap4_rng_data_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .init = omap4_rng_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .cleanup = omap4_rng_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct omap_rng_pdata eip76_rng_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .regs = (u16 *)reg_map_eip76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .data_size = EIP76_RNG_OUTPUT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .data_present = omap4_rng_data_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .init = eip76_rng_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cleanup = omap4_rng_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct of_device_id omap_rng_of_match[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .compatible = "ti,omap2-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .data = &omap2_rng_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .compatible = "ti,omap4-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .data = &omap4_rng_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .compatible = "inside-secure,safexcel-eip76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .data = &eip76_rng_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DEVICE_TABLE(of, omap_rng_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(dev, "no compatible OF match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) priv->pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err = devm_request_irq(dev, irq, omap4_rng_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) IRQF_TRIGGER_NONE, dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "unable to request irq %d, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * On OMAP4, enabling the shutdown_oflo interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * done in the interrupt mask register. There is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * such register on EIP76, and it's enabled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * same bit in the control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (priv->pdata->regs[RNG_INTMASK_REG])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) omap_rng_write(priv, RNG_INTMASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RNG_SHUTDOWN_OFLO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) omap_rng_write(priv, RNG_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) RNG_SHUTDOWN_OFLO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Only OMAP2/3 can be non-DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) omap_rng->pdata = &omap2_rng_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int omap_rng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct omap_rng_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) priv->rng.read = omap_rng_do_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) priv->rng.init = omap_rng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) priv->rng.cleanup = omap_rng_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) priv->rng.quality = 900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) priv->rng.priv = (unsigned long)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (IS_ERR(priv->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) priv->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!priv->rng.name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(&pdev->dev, "Failed to runtime_get device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) priv->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "Unable to enable the clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!IS_ERR(priv->clk_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = clk_prepare_enable(priv->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "Unable to enable the register clk: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) get_omap_rng_device_details(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = devm_hwrng_register(&pdev->dev, &priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_info(&pdev->dev, "Random Number Generator ver. %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) omap_rng_read(priv, RNG_REV_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) priv->base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk_disable_unprepare(priv->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(dev, "initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int omap_rng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct omap_rng_dev *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) priv->pdata->cleanup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk_disable_unprepare(priv->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int __maybe_unused omap_rng_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct omap_rng_dev *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) priv->pdata->cleanup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int __maybe_unused omap_rng_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct omap_rng_dev *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(dev, "Failed to runtime_get device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) priv->pdata->init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct platform_driver omap_rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "omap_rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .pm = &omap_rng_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .of_match_table = of_match_ptr(omap_rng_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .probe = omap_rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .remove = omap_rng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) module_platform_driver(omap_rng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MODULE_ALIAS("platform:omap_rng");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_AUTHOR("Deepak Saxena (and others)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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