^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* n2-drv.c: Niagara-2 RNG driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008, 2011 David S. Miller <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/preempt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "n2rng.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_MODULE_NAME "n2rng"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PFX DRV_MODULE_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_MODULE_VERSION "0.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_MODULE_RELDATE "Jan 7, 2017"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_DESCRIPTION("Niagara2 RNG driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_VERSION(DRV_MODULE_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* The Niagara2 RNG provides a 64-bit read-only random number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * register, plus a control register. Access to the RNG is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * virtualized through the hypervisor so that both guests and control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * nodes can access the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The entropy source consists of raw entropy sources, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * constructed from a voltage controlled oscillator whose phase is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * jittered by thermal noise sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The oscillator in each of the three raw entropy sources run at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * different frequencies. Normally, all three generator outputs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * gathered, xored together, and fed into a CRC circuit, the output of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * which is the 64-bit read-only register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Some time is necessary for all the necessary entropy to build up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * such that a full 64-bits of entropy are available in the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * In normal operating mode (RNG_CTL_LFSR is set), the chip implements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * an interlock which blocks register reads until sufficient entropy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * A control register is provided for adjusting various aspects of RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * operation, and to enable diagnostic modes. Each of the three raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * entropy sources has an enable bit (RNG_CTL_ES{1,2,3}). Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * provided are fields for controlling the minimum time in cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * between read accesses to the register (RNG_CTL_WAIT, this controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * the interlock described in the previous paragraph).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The standard setting is to have the mode bit (RNG_CTL_LFSR) set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * all three entropy sources enabled, and the interlock time set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The CRC polynomial used by the chip is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * P(X) = x64 + x61 + x57 + x56 + x52 + x51 + x50 + x48 + x47 + x46 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * x43 + x42 + x41 + x39 + x38 + x37 + x35 + x32 + x28 + x25 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * x22 + x21 + x17 + x15 + x13 + x12 + x11 + x7 + x5 + x + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * The RNG_CTL_VCO value of each noise cell must be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * separately. This is why 4 control register values must be provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * to the hypervisor. During a write, the hypervisor writes them all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * one at a time, to the actual RNG_CTL register. The first three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * values are used to setup the desired RNG_CTL_VCO for each entropy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * source, for example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * control 0: (1 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * control 1: (2 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * control 2: (3 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * And then the fourth value sets the final chip state and enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int n2rng_hv_err_trans(unsigned long hv_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch (hv_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case HV_EOK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case HV_EWOULDBLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case HV_ENOACCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case HV_EIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case HV_EBUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case HV_EBADALIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case HV_ENORADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned long n2rng_generic_read_control_v2(unsigned long ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long hv_err, state, ticks, watchdog_delta, watchdog_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int block = 0, busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) hv_err = sun4v_rng_ctl_read_v2(ra, unit, &state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &ticks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &watchdog_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &watchdog_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (hv_err == HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (hv_err == HV_EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (++busy >= N2RNG_BUSY_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else if (hv_err == HV_EWOULDBLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (++block >= N2RNG_BLOCK_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __delay(ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* In multi-socket situations, the hypervisor might need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * queue up the RNG control register write if it's for a unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * that is on a cpu socket other than the one we are executing on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * We poll here waiting for a successful read of that control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * register to make sure the write has been actually performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static unsigned long n2rng_control_settle_v2(struct n2rng *np, int unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long ra = __pa(&np->scratch_control[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return n2rng_generic_read_control_v2(ra, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static unsigned long n2rng_write_ctl_one(struct n2rng *np, int unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long control_ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long watchdog_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long *ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (np->hvapi_major == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) hv_err = sun4v_rng_ctl_write_v1(control_ra, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) watchdog_timeout, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hv_err = sun4v_rng_ctl_write_v2(control_ra, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) watchdog_timeout, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (hv_err == HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hv_err = n2rng_control_settle_v2(np, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *ticks = N2RNG_ACCUM_CYCLES_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int n2rng_generic_read_data(unsigned long data_ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long ticks, hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int block = 0, hcheck = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) hv_err = sun4v_rng_data_read(data_ra, &ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (hv_err == HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (hv_err == HV_EWOULDBLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (++block >= N2RNG_BLOCK_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EWOULDBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __delay(ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else if (hv_err == HV_ENOACCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else if (hv_err == HV_EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (++hcheck >= N2RNG_HCHECK_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) udelay(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static unsigned long n2rng_read_diag_data_one(struct n2rng *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long data_ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long *ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (np->hvapi_major == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) hv_err = sun4v_rng_data_read_diag_v1(data_ra, data_len, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) hv_err = sun4v_rng_data_read_diag_v2(data_ra, data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unit, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!*ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *ticks = N2RNG_ACCUM_CYCLES_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int n2rng_generic_read_diag_data(struct n2rng *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long data_ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long ticks, hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) hv_err = n2rng_read_diag_data_one(np, unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data_ra, data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) &ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (hv_err == HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (hv_err == HV_EWOULDBLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (++block >= N2RNG_BLOCK_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -EWOULDBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __delay(ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } else if (hv_err == HV_ENOACCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else if (hv_err == HV_EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int n2rng_generic_write_control(struct n2rng *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long control_ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long hv_err, ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int block = 0, busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) hv_err = n2rng_write_ctl_one(np, unit, state, control_ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) np->wd_timeo, &ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (hv_err == HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (hv_err == HV_EWOULDBLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (++block >= N2RNG_BLOCK_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EWOULDBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __delay(ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else if (hv_err == HV_EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (++busy >= N2RNG_BUSY_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Just try to see if we can successfully access the control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * of the RNG on the domain on which we are currently executing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int n2rng_try_read_ctl(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long hv_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (np->hvapi_major == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hv_err = sun4v_rng_get_diag_ctl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* We purposefully give invalid arguments, HV_NOACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * is higher priority than the errors we'd get from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * these other cases, and that's the error we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * truly interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) hv_err = sun4v_rng_ctl_read_v2(0UL, ~0UL, &x, &x, &x, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (hv_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case HV_EWOULDBLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case HV_ENOACCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hv_err = HV_EOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return n2rng_hv_err_trans(hv_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static u64 n2rng_control_default(struct n2rng *np, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (np->data->chip_version == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = ((2 << RNG_v1_CTL_ASEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v1_CTL_WAIT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RNG_CTL_LFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) switch (ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = ((2 << RNG_v2_CTL_ASEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v2_CTL_WAIT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RNG_CTL_LFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) switch (ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void n2rng_control_swstate_init(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) np->flags |= N2RNG_FLAG_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) np->health_check_sec = N2RNG_HEALTH_CHECK_SEC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) np->accum_cycles = N2RNG_ACCUM_CYCLES_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) np->wd_timeo = N2RNG_WD_TIMEO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 0; i < np->num_units; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct n2rng_unit *up = &np->units[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) up->control[0] = n2rng_control_default(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) up->control[1] = n2rng_control_default(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) up->control[2] = n2rng_control_default(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) up->control[3] = n2rng_control_default(np, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) np->hv_state = HV_RNG_STATE_UNCONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int n2rng_grab_diag_control(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int i, busy_count, err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) busy_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) err = n2rng_try_read_ctl(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (err != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (++busy_count > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&np->op->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "Grab diag control timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int n2rng_init_control(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int err = n2rng_grab_diag_control(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Not in the control domain, that's OK we are only a consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * of the RNG data, we don't setup and program it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (err == -EPERM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) n2rng_control_swstate_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int n2rng_data_read(struct hwrng *rng, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct n2rng *np = (struct n2rng *) rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long ra = __pa(&np->test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!(np->flags & N2RNG_FLAG_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) } else if (np->flags & N2RNG_FLAG_BUFFER_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) np->flags &= ~N2RNG_FLAG_BUFFER_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *data = np->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int err = n2rng_generic_read_data(ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) np->flags |= N2RNG_FLAG_BUFFER_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) np->buffer = np->test_data >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *data = np->test_data & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(&np->op->dev, "RNG error, retesting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) np->flags &= ~N2RNG_FLAG_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!(np->flags & N2RNG_FLAG_SHUTDOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) schedule_delayed_work(&np->work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* On a guest node, just make sure we can read random data properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * If a control node reboots or reloads it's n2rng driver, this won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * work during that time. So we have to keep probing until the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * becomes usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int n2rng_guest_check(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long ra = __pa(&np->test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return n2rng_generic_read_data(ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int n2rng_entropy_diag_read(struct n2rng *np, unsigned long unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u64 *pre_control, u64 pre_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u64 *buffer, unsigned long buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u64 *post_control, u64 post_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long post_ctl_ra = __pa(post_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long pre_ctl_ra = __pa(pre_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned long buffer_ra = __pa(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err = n2rng_generic_write_control(np, pre_ctl_ra, unit, pre_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err = n2rng_generic_read_diag_data(np, unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) buffer_ra, buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) (void) n2rng_generic_write_control(np, post_ctl_ra, unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) post_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static u64 advance_polynomial(u64 poly, u64 val, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int highbit_set = ((s64)val < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (highbit_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val ^= poly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int n2rng_test_buffer_find(struct n2rng *np, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Purposefully skip over the first word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 1; i < SELFTEST_BUFFER_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (np->test_buffer[i] == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void n2rng_dump_test_buffer(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i = 0; i < SELFTEST_BUFFER_WORDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(&np->op->dev, "Test buffer slot %d [0x%016llx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) i, np->test_buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int err, matches, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (np->data->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case N2_n2_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case N2_vf_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case N2_kt_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case N2_m4_rng: /* yes, m4 uses the old value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = RNG_v1_SELFTEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) val = RNG_v2_SELFTEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) matches = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (limit = 0; limit < SELFTEST_LOOPS_MAX; limit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) matches += n2rng_test_buffer_find(np, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (matches >= SELFTEST_MATCH_GOAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = advance_polynomial(SELFTEST_POLY, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (limit >= SELFTEST_LOOPS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(&np->op->dev, "Selftest failed on unit %lu\n", unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) n2rng_dump_test_buffer(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_info(&np->op->dev, "Selftest passed on unit %lu\n", unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int n2rng_control_selftest(struct n2rng *np, unsigned long unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u64 base, base3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (np->data->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case N2_n2_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case N2_vf_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case N2_kt_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) base3 = base | RNG_CTL_LFSR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v1_CTL_WAIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case N2_m4_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) base3 = base | RNG_CTL_LFSR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v2_CTL_WAIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) base3 = base | RNG_CTL_LFSR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) (RNG_v2_SELFTEST_TICKS << RNG_v2_CTL_WAIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) np->test_control[0] = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) np->test_control[1] = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) np->test_control[2] = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) np->test_control[3] = base3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err = n2rng_entropy_diag_read(np, unit, np->test_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) HV_RNG_STATE_HEALTHCHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) np->test_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sizeof(np->test_buffer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) &np->units[unit].control[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) np->hv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return n2rng_check_selftest_buffer(np, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int n2rng_control_check(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 0; i < np->num_units; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int err = n2rng_control_selftest(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* The sanity checks passed, install the final configuration into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * chip, it's ready to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int n2rng_control_configure_units(struct n2rng *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int unit, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) for (unit = 0; unit < np->num_units; unit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct n2rng_unit *up = &np->units[unit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned long ctl_ra = __pa(&up->control[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int esrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u64 base, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (np->data->chip_version == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) (RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RNG_CTL_LFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) shift = RNG_v1_CTL_VCO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RNG_CTL_LFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) shift = RNG_v2_CTL_VCO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* XXX This isn't the best. We should fetch a bunch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * XXX of words using each entropy source combined XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * with each VCO setting, and see which combinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * XXX give the best random data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) for (esrc = 0; esrc < 3; esrc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) up->control[esrc] = base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (esrc << shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (RNG_CTL_ES1 << esrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) up->control[3] = base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) err = n2rng_generic_write_control(np, ctl_ra, unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) HV_RNG_STATE_CONFIGURED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void n2rng_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct n2rng *np = container_of(work, struct n2rng, work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int retries = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!(np->flags & N2RNG_FLAG_CONTROL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) err = n2rng_guest_check(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err = n2rng_control_check(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) err = n2rng_control_configure_units(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) np->flags |= N2RNG_FLAG_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_info(&np->op->dev, "RNG ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (--retries == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(&np->op->dev, "Self-test retries failed, RNG not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else if (err && !(np->flags & N2RNG_FLAG_SHUTDOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) schedule_delayed_work(&np->work, HZ * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void n2rng_driver_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int n2rng_version_printed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (n2rng_version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pr_info("%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const struct of_device_id n2rng_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int n2rng_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct n2rng *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) match = of_match_device(n2rng_match, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) n2rng_driver_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) np = devm_kzalloc(&op->dev, sizeof(*np), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) np->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) np->data = (struct n2rng_template *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) INIT_DELAYED_WORK(&np->work, n2rng_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (np->data->multi_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) np->flags |= N2RNG_FLAG_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) np->hvapi_major = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (sun4v_hvapi_register(HV_GRP_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) np->hvapi_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &np->hvapi_minor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) np->hvapi_major = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (sun4v_hvapi_register(HV_GRP_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) np->hvapi_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) &np->hvapi_minor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(&op->dev, "Cannot register suitable "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "HVAPI version.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (np->flags & N2RNG_FLAG_MULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (np->hvapi_major < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(&op->dev, "multi-unit-capable RNG requires "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "HVAPI major version 2 or later, got %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) np->hvapi_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto out_hvapi_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) np->num_units = of_getintprop_default(op->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "rng-#units", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!np->num_units) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(&op->dev, "VF RNG lacks rng-#units property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) goto out_hvapi_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) np->num_units = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) np->hvapi_major, np->hvapi_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) np->units = devm_kcalloc(&op->dev, np->num_units, sizeof(*np->units),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!np->units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) goto out_hvapi_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err = n2rng_init_control(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto out_hvapi_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_info(&op->dev, "Found %s RNG, units: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ((np->flags & N2RNG_FLAG_MULTI) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "multi-unit-capable" : "single-unit"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) np->num_units);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) np->hwrng.name = DRV_MODULE_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) np->hwrng.data_read = n2rng_data_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) np->hwrng.priv = (unsigned long) np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) err = devm_hwrng_register(&op->dev, &np->hwrng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto out_hvapi_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) platform_set_drvdata(op, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) schedule_delayed_work(&np->work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) out_hvapi_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) sun4v_hvapi_unregister(HV_GRP_RNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int n2rng_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct n2rng *np = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) np->flags |= N2RNG_FLAG_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) cancel_delayed_work_sync(&np->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) sun4v_hvapi_unregister(HV_GRP_RNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct n2rng_template n2_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .id = N2_n2_rng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .multi_capable = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .chip_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static struct n2rng_template vf_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .id = N2_vf_rng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .multi_capable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .chip_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct n2rng_template kt_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .id = N2_kt_rng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .multi_capable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .chip_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct n2rng_template m4_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .id = N2_m4_rng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .multi_capable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .chip_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct n2rng_template m7_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .id = N2_m7_rng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .multi_capable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .chip_version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct of_device_id n2rng_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "random-number-generator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .compatible = "SUNW,n2-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .data = &n2_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .name = "random-number-generator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .compatible = "SUNW,vf-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .data = &vf_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .name = "random-number-generator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .compatible = "SUNW,kt-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .data = &kt_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = "random-number-generator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .compatible = "ORCL,m4-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .data = &m4_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "random-number-generator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .compatible = "ORCL,m7-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .data = &m7_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_DEVICE_TABLE(of, n2rng_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static struct platform_driver n2rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .name = "n2rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .of_match_table = n2rng_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .probe = n2rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .remove = n2rng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) module_platform_driver(n2rng_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags