^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RNG driver for Freescale RNGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alan Carvalho de Assis <acassis@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver is based on other RNG drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* RNGA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RNGA_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RNGA_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RNGA_ENTROPY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RNGA_OUTPUT_FIFO 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RNGA_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RNGA_VERIFICATION_CONTROL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RNGA_OSC_CONTROL_COUNTER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RNGA_OSC1_COUNTER 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RNGA_OSC2_COUNTER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RNGA_OSC_COUNTER_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* RNGA Registers Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RNG_ADDR_RANGE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* RNGA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RNGA_CONTROL_SLEEP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RNGA_CONTROL_CLEAR_INT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RNGA_CONTROL_MASK_INTS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RNGA_CONTROL_GO 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RNGA_STATUS_LEVEL_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* RNGA Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RNGA_STATUS_OSC_DEAD 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RNGA_STATUS_SLEEP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RNGA_STATUS_ERROR_INT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RNGA_STATUS_FIFO_UNDERFLOW 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RNGA_STATUS_LAST_READ_STATUS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RNGA_STATUS_SECURITY_VIOLATION 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct mxc_rng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int mxc_rnga_data_present(struct hwrng *rng, int wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mxc_rng *mxc_rng = container_of(rng, struct mxc_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* how many random numbers are in FIFO? [0-16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RNGA_STATUS_LEVEL_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (level || !wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return !!level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int mxc_rnga_data_read(struct hwrng *rng, u32 * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mxc_rng *mxc_rng = container_of(rng, struct mxc_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* retrieve a random number from FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* some error while reading this random number? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* if error: clear error interrupt, but doesn't return random number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_dbg(mxc_rng->dev, "Error while reading random number!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int mxc_rnga_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 ctrl, osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct mxc_rng *mxc_rng = container_of(rng, struct mxc_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* verify if oscillator is working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) osc = __raw_readl(mxc_rng->mem + RNGA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (osc & RNGA_STATUS_OSC_DEAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(mxc_rng->dev, "RNGA Oscillator is dead!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* go running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __raw_writel(ctrl | RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void mxc_rnga_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mxc_rng *mxc_rng = container_of(rng, struct mxc_rng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* stop rnga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __raw_writel(ctrl & ~RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init mxc_rnga_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mxc_rng *mxc_rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mxc_rng = devm_kzalloc(&pdev->dev, sizeof(*mxc_rng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!mxc_rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mxc_rng->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mxc_rng->rng.name = "mxc-rnga";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mxc_rng->rng.init = mxc_rnga_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mxc_rng->rng.cleanup = mxc_rnga_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mxc_rng->rng.data_present = mxc_rnga_data_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mxc_rng->rng.data_read = mxc_rnga_data_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mxc_rng->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (IS_ERR(mxc_rng->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(&pdev->dev, "Could not get rng_clk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return PTR_ERR(mxc_rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) err = clk_prepare_enable(mxc_rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mxc_rng->mem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (IS_ERR(mxc_rng->mem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err = PTR_ERR(mxc_rng->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) err = hwrng_register(&mxc_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(&pdev->dev, "MXC RNGA registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk_disable_unprepare(mxc_rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __exit mxc_rnga_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mxc_rng *mxc_rng = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) hwrng_unregister(&mxc_rng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk_disable_unprepare(mxc_rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct of_device_id mxc_rnga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .compatible = "fsl,imx21-rnga", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .compatible = "fsl,imx31-rnga", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_DEVICE_TABLE(of, mxc_rnga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct platform_driver mxc_rnga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "mxc_rnga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .of_match_table = mxc_rnga_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .remove = __exit_p(mxc_rnga_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) module_platform_driver_probe(mxc_rnga_driver, mxc_rnga_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DESCRIPTION("H/W RNGA driver for i.MX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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