^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ingenic True Random Number Generator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* DTRNG register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TRNG_REG_CFG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TRNG_REG_RANDOMNUM_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TRNG_REG_STATUS_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* bits within the CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CFG_RDY_CLR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_INT_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CFG_GEN_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* bits within the STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STATUS_RANDOM_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ingenic_trng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int ingenic_trng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ctrl |= CFG_GEN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void ingenic_trng_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ctrl &= ~CFG_GEN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int ingenic_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct ingenic_trng *trng = container_of(rng, struct ingenic_trng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = readl_poll_timeout(trng->base + TRNG_REG_STATUS_OFFSET, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) status & STATUS_RANDOM_RDY, 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_err("%s: Wait for DTRNG data ready timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *data = readl(trng->base + TRNG_REG_RANDOMNUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int ingenic_trng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ingenic_trng *trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) trng->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (IS_ERR(trng->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_err("%s: Failed to map DTRNG registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = PTR_ERR(trng->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return PTR_ERR(trng->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) trng->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (IS_ERR(trng->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = PTR_ERR(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pr_crit("%s: Cannot get DTRNG clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return PTR_ERR(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = clk_prepare_enable(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pr_crit("%s: Unable to enable DTRNG clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) trng->rng.name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) trng->rng.init = ingenic_trng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) trng->rng.cleanup = ingenic_trng_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) trng->rng.read = ingenic_trng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = hwrng_register(&trng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(&pdev->dev, "Failed to register hwrng\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err_unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) platform_set_drvdata(pdev, trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_info(&pdev->dev, "Ingenic DTRNG driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err_unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int ingenic_trng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ingenic_trng *trng = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) hwrng_unregister(&trng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ctrl &= ~CFG_GEN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct of_device_id ingenic_trng_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .compatible = "ingenic,x1830-dtrng" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DEVICE_TABLE(of, ingenic_trng_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct platform_driver ingenic_trng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .probe = ingenic_trng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .remove = ingenic_trng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "ingenic-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .of_match_table = ingenic_trng_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module_platform_driver(ingenic_trng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_DESCRIPTION("Ingenic True Random Number Generator driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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