^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RNG driver for Freescale RNGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RNGC_VER_ID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RNGC_COMMAND 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RNGC_CONTROL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RNGC_STATUS 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RNGC_ERROR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RNGC_FIFO 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* the fields in the ver id register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RNGC_TYPE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RNGC_VER_MAJ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* the rng_type field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RNGC_TYPE_RNGB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RNGC_TYPE_RNGC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RNGC_CMD_CLR_ERR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RNGC_CMD_CLR_INT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RNGC_CMD_SEED 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RNGC_CMD_SELF_TEST 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RNGC_CTRL_MASK_ERROR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RNGC_CTRL_MASK_DONE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RNGC_CTRL_AUTO_SEED 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RNGC_STATUS_ERROR 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RNGC_STATUS_SEED_DONE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RNGC_STATUS_ST_DONE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RNGC_TIMEOUT 3000 /* 3 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static bool self_test = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) module_param(self_test, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct imx_rngc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct completion rng_op_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * err_reg is written only by the irq handler and read only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * when interrupts are masked, we need no spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 err_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 ctrl, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* mask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ctrl = readl(rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(ctrl, rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * CLR_INT clears the interrupt only if there's no error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * CLR_ERR clear the interrupt and the error register if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * is an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cmd = readl(rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(cmd, rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ctrl = readl(rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(ctrl, rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int imx_rngc_self_test(struct imx_rngc *rngc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) imx_rngc_irq_unmask(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* run self test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cmd = readl(rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) imx_rngc_irq_mask_clear(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return rngc->err_reg ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) while (max >= sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) status = readl(rngc->base + RNGC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* is there some error while reading this random number? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (status & RNGC_STATUS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* how many random numbers are in FIFO? [0-16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) RNGC_STATUS_FIFO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* retrieve a random number from FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *(u32 *)data = readl(rngc->base + RNGC_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) retval += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) max -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return retval ? retval : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t imx_rngc_irq(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct imx_rngc *rngc = (struct imx_rngc *)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * clearing the interrupt will also clear the error register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * read error and status before clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) status = readl(rngc->base + RNGC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rngc->err_reg = readl(rngc->base + RNGC_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) imx_rngc_irq_mask_clear(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) complete(&rngc->rng_op_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int imx_rngc_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 cmd, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* clear error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cmd = readl(rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) imx_rngc_irq_unmask(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* create seed, repeat while there is some statistical error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* seed creation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cmd = readl(rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = wait_for_completion_timeout(&rngc->rng_op_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) RNGC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (rngc->err_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * enable automatic seeding, the rngc creates a new seed automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * after serving 2^20 random 160-bit words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ctrl = readl(rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctrl |= RNGC_CTRL_AUTO_SEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(ctrl, rngc->base + RNGC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * if initialisation was successful, we keep the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * unmasked until imx_rngc_cleanup is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * we mask the interrupt ourselves if we return an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) imx_rngc_irq_mask_clear(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void imx_rngc_cleanup(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) imx_rngc_irq_mask_clear(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int imx_rngc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct imx_rngc *rngc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 ver_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 rng_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!rngc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rngc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (IS_ERR(rngc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return PTR_ERR(rngc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rngc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (IS_ERR(rngc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(&pdev->dev, "Can not get rng_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PTR_ERR(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = clk_prepare_enable(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ver_id = readl(rngc->base + RNGC_VER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rng_type = ver_id >> RNGC_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * This driver supports only RNGC and RNGB. (There's a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * driver for RNGA.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(rngc->dev, "Can't get interrupt working.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) init_completion(&rngc->rng_op_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rngc->rng.name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rngc->rng.init = imx_rngc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rngc->rng.read = imx_rngc_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rngc->rng.cleanup = imx_rngc_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rngc->rng.quality = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rngc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) platform_set_drvdata(pdev, rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) imx_rngc_irq_mask_clear(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (self_test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = imx_rngc_self_test(rngc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(rngc->dev, "self test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = hwrng_register(&rngc->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(&pdev->dev, "hwrng registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Freescale RNG%c registered (HW revision %d.%02d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rng_type == RNGC_TYPE_RNGB ? 'B' : 'C',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (ver_id >> RNGC_VER_MAJ_SHIFT) & 0xff, ver_id & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_disable_unprepare(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int __exit imx_rngc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct imx_rngc *rngc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hwrng_unregister(&rngc->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk_disable_unprepare(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int __maybe_unused imx_rngc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct imx_rngc *rngc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clk_disable_unprepare(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int __maybe_unused imx_rngc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct imx_rngc *rngc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_prepare_enable(rngc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SIMPLE_DEV_PM_OPS(imx_rngc_pm_ops, imx_rngc_suspend, imx_rngc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct of_device_id imx_rngc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { .compatible = "fsl,imx25-rngb", .data = NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct platform_driver imx_rngc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "imx_rngc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .pm = &imx_rngc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .of_match_table = imx_rngc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .remove = __exit_p(imx_rngc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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