^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RNG driver for Exynos TRNGs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Łukasz Stelmach <l.stelmach@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2017 (c) Samsung Electronics Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Krzysztof Kozłowski <krzk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EXYNOS_TRNG_CLKDIV (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EXYNOS_TRNG_CTRL (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EXYNOS_TRNG_CTRL_RNGEN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EXYNOS_TRNG_POST_CTRL (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EXYNOS_TRNG_ONLINE_CTRL (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXYNOS_TRNG_ONLINE_STAT (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS_TRNG_FIFO_CTRL (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXYNOS_TRNG_FIFO_0 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EXYNOS_TRNG_FIFO_1 (0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EXYNOS_TRNG_FIFO_2 (0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXYNOS_TRNG_FIFO_3 (0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS_TRNG_FIFO_4 (0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXYNOS_TRNG_FIFO_5 (0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXYNOS_TRNG_FIFO_6 (0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS_TRNG_FIFO_7 (0x9c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXYNOS_TRNG_FIFO_LEN (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXYNOS_TRNG_CLOCK_RATE (500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct exynos_trng_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct exynos_trng_dev *trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) trng = (struct exynos_trng_dev *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val == 0, 200, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int exynos_trng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long sss_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sss_rate = clk_get_rate(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * For most TRNG circuits the clock frequency of under 500 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * is safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (val > 0x7fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(trng->dev, "clock divider too large: %d", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val = val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Enable the generator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = EXYNOS_TRNG_CTRL_RNGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Disable post-processing. /dev/hwrng is supposed to deliver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * unprocessed data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int exynos_trng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct exynos_trng_dev *trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!trng->rng.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) trng->rng.init = exynos_trng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) trng->rng.read = exynos_trng_do_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) trng->rng.priv = (unsigned long) trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) platform_set_drvdata(pdev, trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) trng->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) trng->mem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ERR(trng->mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PTR_ERR(trng->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = pm_runtime_resume_and_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(&pdev->dev, "Could not get runtime PM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) goto err_pm_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) trng->clk = devm_clk_get(&pdev->dev, "secss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(trng->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = PTR_ERR(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(&pdev->dev, "Could not get clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto err_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = clk_prepare_enable(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(&pdev->dev, "Could not enable the clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto err_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = devm_hwrng_register(&pdev->dev, &trng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(&pdev->dev, "Could not register hwrng device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_info(&pdev->dev, "Exynos True Random Number Generator.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err_pm_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int exynos_trng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct exynos_trng_dev *trng = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int __maybe_unused exynos_trng_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int __maybe_unused exynos_trng_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dev, "Could not get runtime PM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) exynos_trng_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct of_device_id exynos_trng_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .compatible = "samsung,exynos5250-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_DEVICE_TABLE(of, exynos_trng_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct platform_driver exynos_trng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "exynos-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .pm = &exynos_trng_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .of_match_table = exynos_trng_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .probe = exynos_trng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .remove = exynos_trng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) module_platform_driver(exynos_trng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_AUTHOR("Łukasz Stelmach");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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