^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define POWER_DOWN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define POWER_DOWN_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* hwrng quality: bits of true entropy per 1024 bits of input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CC_TRNG_QUALITY 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* CryptoCell TRNG HW definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CC_TRNG_NUM_OF_ROSCS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* The number of words generated in the entropy holding register (EHR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 6 words (192 bit) according to HW implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CC_TRNG_EHR_IN_WORDS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* RNG interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) // BLOCK: RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CC_RNG_IMR_REG_OFFSET 0x0100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CC_RNG_ISR_REG_OFFSET 0x0104UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CC_RNG_ICR_REG_OFFSET 0x0108UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) // BLOCK: SEC_HOST_RGF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) // BLOCK: NVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) // --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags