^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "cctrng.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CC_REG_LOW(name) (name ## _BIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CC_REG_FLD_GET(reg_name, fld_name, reg_val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (FIELD_GET(CC_GENMASK(CC_ ## reg_name ## _ ## fld_name), reg_val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CC_HW_RESET_LOOP_COUNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CC_TRNG_SUSPEND_TIMEOUT 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* data circular buffer in words must be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - of a power-of-2 size (limitation of circ_buf.h macros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - at least 6, the size generated in the EHR according to HW implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCTRNG_DATA_BUF_WORDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* The timeout for the TRNG operation should be calculated with the formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Timeout = EHR_NUM * VN_COEFF * EHR_LENGTH * SAMPLE_CNT * SCALE_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * while:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - SAMPLE_CNT is input value from the characterisation process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - all the rest are constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EHR_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VN_COEFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EHR_LENGTH CC_TRNG_EHR_IN_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCALE_VALUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCTRNG_TIMEOUT(smpl_cnt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (EHR_NUM * VN_COEFF * EHR_LENGTH * smpl_cnt * SCALE_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct cctrng_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *cc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 active_rosc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Sampling interval for each ring oscillator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * count of ring oscillator cycles between consecutive bits sampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Value of 0 indicates non-valid rosc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 smpl_ratio[CC_TRNG_NUM_OF_ROSCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 data_buf[CCTRNG_DATA_BUF_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct circ_buf circ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct work_struct compwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct work_struct startwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* pending_hw - 1 when HW is pending, 0 when it is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) atomic_t pending_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* protects against multiple concurrent consumers of data_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) spinlock_t read_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* functions for write/read CC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline void cc_iowrite(struct cctrng_drvdata *drvdata, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) iowrite32(val, (drvdata->cc_base + reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline u32 cc_ioread(struct cctrng_drvdata *drvdata, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ioread32(drvdata->cc_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int cc_trng_pm_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rc = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* pm_runtime_get_sync() can return 1 as a valid return code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return (rc == 1 ? 0 : rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void cc_trng_pm_put_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rc = pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(dev, "pm_runtime_put_autosuspend returned %x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int cc_trng_pm_init(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* must be before the enabling to avoid redundant suspending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pm_runtime_set_autosuspend_delay(dev, CC_TRNG_SUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* set us as active - note we won't do PM ops until cc_trng_pm_go()! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void cc_trng_pm_go(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* enable the PM module*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void cc_trng_pm_fini(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline int cc_trng_parse_sampling_ratio(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct device_node *np = drvdata->pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* ret will be set to 0 if at least one rosc has (sampling ratio > 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rc = of_property_read_u32_array(np, "arm,rosc-ratio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) drvdata->smpl_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CC_TRNG_NUM_OF_ROSCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* arm,rosc-ratio was not found in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* verify that at least one rosc has (sampling ratio > 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 0; i < CC_TRNG_NUM_OF_ROSCS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(dev, "rosc %d sampling ratio %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) i, drvdata->smpl_ratio[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (drvdata->smpl_ratio[i] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int cc_trng_change_rosc(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(dev, "cctrng change rosc (was %d)\n", drvdata->active_rosc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) drvdata->active_rosc += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) while (drvdata->active_rosc < CC_TRNG_NUM_OF_ROSCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (drvdata->smpl_ratio[drvdata->active_rosc] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) drvdata->active_rosc += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void cc_trng_enable_rnd_source(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 max_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Set watchdog threshold to maximal allowed time (in CPU cycles) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) max_cycles = CCTRNG_TIMEOUT(drvdata->smpl_ratio[drvdata->active_rosc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cc_iowrite(drvdata, CC_RNG_WATCHDOG_VAL_REG_OFFSET, max_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* enable the RND source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* unmask RNG interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, (u32)~CC_RNG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* increase circular data buffer index (head/tail) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void circ_idx_inc(int *idx, int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *idx += (bytes + 3) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *idx &= (CCTRNG_DATA_BUF_WORDS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline size_t circ_buf_space(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return CIRC_SPACE(drvdata->circ.head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int cctrng_read(struct hwrng *rng, void *data, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* current implementation ignores "wait" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 *buf = (u32 *)drvdata->circ.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) size_t copied = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) size_t cnt_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) size_t left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!spin_trylock(&drvdata->read_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* concurrent consumers from data_buf cannot be served */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_dbg_ratelimited(dev, "unable to hold lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* copy till end of data buffer (without wrap back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cnt_w = CIRC_CNT_TO_END(drvdata->circ.head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) size = min((cnt_w<<2), max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) memcpy(data, &(buf[drvdata->circ.tail]), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) copied = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) circ_idx_inc(&drvdata->circ.tail, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* copy rest of data in data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) left = max - copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cnt_w = CIRC_CNT(drvdata->circ.head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) size = min((cnt_w<<2), left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) memcpy(data, &(buf[drvdata->circ.tail]), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) copied += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) circ_idx_inc(&drvdata->circ.tail, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_unlock(&drvdata->read_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* re-check space in buffer to avoid potential race */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* increment device's usage counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int rc = cc_trng_pm_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "cc_trng_pm_get returned %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* schedule execution of deferred work handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * for filling of data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) schedule_work(&drvdata->startwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) atomic_set(&drvdata->pending_hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 tmp_smpl_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(dev, "cctrng hw trigger.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* enable the HW RND clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* do software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cc_iowrite(drvdata, CC_RNG_SW_RESET_REG_OFFSET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* in order to verify that the reset has completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * the sample count need to be verified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* enable the HW RND clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* set sampling ratio (rng_clocks) between consecutive bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cc_iowrite(drvdata, CC_SAMPLE_CNT1_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) drvdata->smpl_ratio[drvdata->active_rosc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* read the sampling ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmp_smpl_cnt = cc_ioread(drvdata, CC_SAMPLE_CNT1_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } while (tmp_smpl_cnt != drvdata->smpl_ratio[drvdata->active_rosc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* disable the RND source for setting new parameters in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cc_iowrite(drvdata, CC_TRNG_CONFIG_REG_OFFSET, drvdata->active_rosc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Debug Control register: set to 0 - no bypasses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cc_iowrite(drvdata, CC_TRNG_DEBUG_CONTROL_REG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cc_trng_enable_rnd_source(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void cc_trng_compwork_handler(struct work_struct *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 isr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 ehr_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct cctrng_drvdata *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) container_of(w, struct cctrng_drvdata, compwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* stop DMA and the RNG source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cc_iowrite(drvdata, CC_RNG_DMA_ENABLE_REG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* read RNG_ISR and check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) isr = cc_ioread(drvdata, CC_RNG_ISR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ehr_valid = CC_REG_FLD_GET(RNG_ISR, EHR_VALID, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_dbg(dev, "Got RNG_ISR=0x%08X (EHR_VALID=%u)\n", isr, ehr_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (fips_enabled && CC_REG_FLD_GET(RNG_ISR, CRNGT_ERR, isr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fips_fail_notify();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* FIPS error is fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) panic("Got HW CRNGT error while fips is enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Clear all pending RNG interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!ehr_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* in case of AUTOCORR/TIMEOUT error, try the next ROSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (CC_REG_FLD_GET(RNG_ISR, AUTOCORR_ERR, isr) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CC_REG_FLD_GET(RNG_ISR, WATCHDOG, isr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_dbg(dev, "cctrng autocorr/timeout error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto next_rosc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* in case of VN error, ignore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* read EHR data from registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < CC_TRNG_EHR_IN_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* calc word ptr in data_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 *buf = (u32 *)drvdata->circ.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf[drvdata->circ.head] = cc_ioread(drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) CC_EHR_DATA_0_REG_OFFSET + (i*sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* EHR_DATA registers are cleared on read. In case 0 value was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * returned, restart the entropy collection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (buf[drvdata->circ.head] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(dev, "Got 0 value in EHR. active_rosc %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) drvdata->active_rosc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto next_rosc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) circ_idx_inc(&drvdata->circ.head, 1<<2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) atomic_set(&drvdata->pending_hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* continue to fill data buffer if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Re-enable rnd source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cc_trng_enable_rnd_source(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cc_trng_pm_put_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_dbg(dev, "compwork handler done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) next_rosc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (cc_trng_change_rosc(drvdata) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* trigger trng hw with next rosc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cc_trng_hw_trigger(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) atomic_set(&drvdata->pending_hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cc_trng_pm_put_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static irqreturn_t cc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 irr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* if driver suspended return, probably shared interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* read the interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) irr = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_dbg(dev, "Got IRR=0x%08X\n", irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (irr == 0) /* Probably shared interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* clear interrupt - must be before processing events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* RNG interrupt - most probable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (irr & CC_HOST_RNG_IRQ_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Mask RNG interrupts - will be unmasked in deferred work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* We clear RNG interrupt here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * to avoid it from firing as we'll unmask RNG interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CC_HOST_RNG_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) irr &= ~CC_HOST_RNG_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* schedule execution of deferred work handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) schedule_work(&drvdata->compwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (irr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "IRR includes unknown cause bits (0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Just warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void cc_trng_startwork_handler(struct work_struct *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct cctrng_drvdata *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) container_of(w, struct cctrng_drvdata, startwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) drvdata->active_rosc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cc_trng_hw_trigger(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int cc_trng_clk_init(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct device *dev = &(drvdata->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk = devm_clk_get_optional(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return dev_err_probe(dev, PTR_ERR(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "Error getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) drvdata->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rc = clk_prepare_enable(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void cc_trng_clk_fini(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int cctrng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct resource *req_mem_cc_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct cctrng_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) drvdata->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!drvdata->rng.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) drvdata->rng.read = cctrng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) drvdata->rng.priv = (unsigned long)drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) drvdata->rng.quality = CC_TRNG_QUALITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) drvdata->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) drvdata->circ.buf = (char *)drvdata->data_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Get device resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* First CC registers space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) req_mem_cc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Map registers space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (IS_ERR(drvdata->cc_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(dev, "Failed to ioremap registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return PTR_ERR(drvdata->cc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) req_mem_cc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &req_mem_cc_regs->start, drvdata->cc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Then IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(dev, "Failed getting IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* parse sampling rate from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rc = cc_trng_parse_sampling_ratio(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dev, "Failed to get legal sampling ratio for rosc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rc = cc_trng_clk_init(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev, "cc_trng_clk_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) spin_lock_init(&drvdata->read_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* register the driver isr function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(dev, "Could not register to interrupt %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto post_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_dbg(dev, "Registered to IRQ: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_dbg(dev, "IRR=0x%08X\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* unmask HOST RNG interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ~CC_HOST_RNG_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* init PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rc = cc_trng_pm_init(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "cc_trng_pm_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto post_clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* increment device's usage counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rc = cc_trng_pm_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(dev, "cc_trng_pm_get returned %x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto post_pm_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* set pending_hw to verify that HW won't be triggered from read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) atomic_set(&drvdata->pending_hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* registration of the hwrng device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rc = hwrng_register(&drvdata->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(dev, "Could not register hwrng device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto post_pm_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* trigger HW to start generate data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) drvdata->active_rosc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cc_trng_hw_trigger(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* All set, we can allow auto-suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cc_trng_pm_go(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_info(dev, "ARM cctrng device initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) post_pm_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) cc_trng_pm_fini(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) post_clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cc_trng_clk_fini(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int cctrng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct cctrng_drvdata *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_dbg(dev, "Releasing cctrng resources...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) hwrng_unregister(&drvdata->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cc_trng_pm_fini(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cc_trng_clk_fini(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_info(dev, "ARM cctrng device terminated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int __maybe_unused cctrng_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) POWER_DOWN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static bool cctrng_wait_for_reset_completion(struct cctrng_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* in cc7x3 NVM_IS_IDLE indicates that CC reset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * completed and device is fully functional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) val = cc_ioread(drvdata, CC_NVM_IS_IDLE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (val & BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* hw indicate reset completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* allow scheduling other process on the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* reset not completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int __maybe_unused cctrng_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Enables the device source clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) rc = clk_prepare_enable(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "failed getting clock back on. We're toast.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* wait for Cryptocell reset completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!cctrng_wait_for_reset_completion(drvdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(dev, "Cryptocell reset not completed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* unmask HOST RNG interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ~CC_HOST_RNG_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) POWER_DOWN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static UNIVERSAL_DEV_PM_OPS(cctrng_pm, cctrng_suspend, cctrng_resume, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct of_device_id arm_cctrng_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { .compatible = "arm,cryptocell-713-trng", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { .compatible = "arm,cryptocell-703-trng", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MODULE_DEVICE_TABLE(of, arm_cctrng_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct platform_driver cctrng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "cctrng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .of_match_table = arm_cctrng_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .pm = &cctrng_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .probe = cctrng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .remove = cctrng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int __init cctrng_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Compile time assertion checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) BUILD_BUG_ON(CCTRNG_DATA_BUF_WORDS < 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) BUILD_BUG_ON((CCTRNG_DATA_BUF_WORDS & (CCTRNG_DATA_BUF_WORDS-1)) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return platform_driver_register(&cctrng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) module_init(cctrng_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void __exit cctrng_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) platform_driver_unregister(&cctrng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) module_exit(cctrng_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Module description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MODULE_DESCRIPTION("ARM CryptoCell TRNG Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MODULE_AUTHOR("ARM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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