^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hardware Random Number Generator support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Cavium Thunder, Marvell OcteonTx/Tx2 processor families.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/arch_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* PCI device IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_DEVID_CAVIUM_RNG_PF 0xA018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVID_CAVIUM_RNG_VF 0xA033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HEALTH_STATUS_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* RST device info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_DEVICE_ID_RST_OTX2 0xA085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RST_BOOT_REG 0x1600ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLOCK_BASE_RATE 50000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSEC_TO_NSEC(x) (x * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cavium_rng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct hwrng ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *pf_regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u64 clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u64 prev_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 prev_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline bool is_octeontx(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX_83XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MIDR_CPU_VAR_REV(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MIDR_CPU_VAR_REV(3, 0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX_81XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MIDR_CPU_VAR_REV(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MIDR_CPU_VAR_REV(3, 0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MIDR_CPU_VAR_REV(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MIDR_CPU_VAR_REV(3, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u64 rng_get_coprocessor_clkrate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u64 ret = CLOCK_BASE_RATE * 16; /* Assume 800Mhz as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PCI_DEVICE_ID_RST_OTX2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) base = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) goto error_put_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* RST: PNR_MUL * 50Mhz gives clockrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = CLOCK_BASE_RATE * ((readq(base + RST_BOOT_REG) >> 33) & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) error_put_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int check_rng_health(struct cavium_rng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u64 cur_err, cur_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 status, cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u64 time_elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Skip checking health for OcteonTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!rng->pf_regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) status = readq(rng->pf_regbase + HEALTH_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (status & BIT_ULL(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(&rng->pdev->dev, "HWRNG: Startup health test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cycles = status >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cur_time = arch_timer_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* RNM_HEALTH_STATUS[CYCLES_SINCE_HEALTH_FAILURE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Number of coprocessor cycles times 2 since the last failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * This field doesn't get cleared/updated until another failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cycles = cycles / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cur_err = (cycles * 1000000000) / rng->clock_rate; /* In nanosec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Ignore errors that happenned a long time ago, these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * are most likely false positive errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (cur_err > MSEC_TO_NSEC(10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rng->prev_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rng->prev_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rng->prev_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Calculate time elapsed since last error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * '1' tick of CNTVCT is 10ns, since it runs at 100Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) time_elapsed = (cur_time - rng->prev_time) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) time_elapsed += rng->prev_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Check if current error is a new one or the old one itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * If error is a new one then consider there is a persistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * issue with entropy, declare hardware failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (cur_err < time_elapsed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(&rng->pdev->dev, "HWRNG failure detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rng->prev_error = cur_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rng->prev_time = cur_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rng->prev_error = cur_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rng->prev_time = cur_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Read data from the RNG unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int cavium_rng_read(struct hwrng *rng, void *dat, size_t max, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct cavium_rng *p = container_of(rng, struct cavium_rng, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int size = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) err = check_rng_health(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while (size >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *((u64 *)dat) = readq(p->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) size -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dat += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *((u8 *)dat) = readb(p->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dat++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int cavium_map_pf_regs(struct cavium_rng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Health status is not supported on 83xx, skip mapping PF CSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (is_octeontx(rng->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rng->pf_regbase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PCI_DEVID_CAVIUM_RNG_PF, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(&pdev->dev, "Cannot find RNG PF device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rng->pf_regbase = ioremap(pci_resource_start(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!rng->pf_regbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(&pdev->dev, "Failed to map PF CSR region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Get co-processor clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rng->clock_rate = rng_get_coprocessor_clkrate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Map Cavium RNG to an HWRNG object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int cavium_rng_probe_vf(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct cavium_rng *rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rng->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Map the RNG result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rng->result = pcim_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!rng->result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(&pdev->dev, "Error iomap failed retrieving result.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rng->ops.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "cavium-rng-%s", dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!rng->ops.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rng->ops.read = cavium_rng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rng->ops.quality = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_set_drvdata(pdev, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Health status is available only at PF, hence map PF registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = cavium_map_pf_regs(rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = devm_hwrng_register(&pdev->dev, &rng->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(&pdev->dev, "Error registering device as HWRNG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Remove the VF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void cavium_rng_remove_vf(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct cavium_rng *rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rng = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iounmap(rng->pf_regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct pci_device_id cavium_rng_vf_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CAVIUM_RNG_VF) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_DEVICE_TABLE(pci, cavium_rng_vf_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct pci_driver cavium_rng_vf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "cavium_rng_vf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .id_table = cavium_rng_vf_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .probe = cavium_rng_probe_vf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .remove = cavium_rng_remove_vf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_pci_driver(cavium_rng_vf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Omer Khaliq <okhaliq@caviumnetworks.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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