^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2011 Peter Korsgaard <jacmet@sunsite.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TRNG_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TRNG_MR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TRNG_ISR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TRNG_ODATA 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TRNG_KEY 0x524e4700 /* RNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TRNG_HALFR BIT(0) /* generate RN every 168 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct atmel_trng_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool has_half_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct atmel_trng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int atmel_trng_read(struct hwrng *rng, void *buf, size_t max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct atmel_trng *trng = container_of(rng, struct atmel_trng, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* data ready? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (readl(trng->base + TRNG_ISR) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *data = readl(trng->base + TRNG_ODATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ensure data ready is only set again AFTER the next data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) word is ready in case it got set between checking ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) and reading ODATA, so we don't risk re-reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) same word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) readl(trng->base + TRNG_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void atmel_trng_enable(struct atmel_trng *trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel(TRNG_KEY | 1, trng->base + TRNG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void atmel_trng_disable(struct atmel_trng *trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(TRNG_KEY, trng->base + TRNG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int atmel_trng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct atmel_trng *trng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct atmel_trng_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!trng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) trng->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (IS_ERR(trng->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return PTR_ERR(trng->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) trng->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (IS_ERR(trng->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return PTR_ERR(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (data->has_half_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long rate = clk_get_rate(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* if peripheral clk is above 100MHz, set HALFR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (rate > 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(TRNG_HALFR, trng->base + TRNG_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = clk_prepare_enable(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) atmel_trng_enable(trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) trng->rng.name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) trng->rng.read = atmel_trng_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = devm_hwrng_register(&pdev->dev, &trng->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) platform_set_drvdata(pdev, trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) atmel_trng_disable(trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int atmel_trng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct atmel_trng *trng = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) atmel_trng_disable(trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int atmel_trng_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct atmel_trng *trng = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) atmel_trng_disable(trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_disable_unprepare(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int atmel_trng_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct atmel_trng *trng = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = clk_prepare_enable(trng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) atmel_trng_enable(trng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct dev_pm_ops atmel_trng_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .suspend = atmel_trng_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .resume = atmel_trng_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct atmel_trng_data at91sam9g45_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .has_half_rate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct atmel_trng_data sam9x60_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .has_half_rate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct of_device_id atmel_trng_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .compatible = "atmel,at91sam9g45-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .data = &at91sam9g45_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .compatible = "microchip,sam9x60-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .data = &sam9x60_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(of, atmel_trng_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct platform_driver atmel_trng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .probe = atmel_trng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .remove = atmel_trng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "atmel-trng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pm = &atmel_trng_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .of_match_table = atmel_trng_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) module_platform_driver(atmel_trng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DESCRIPTION("Atmel true random number generator driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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