^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * VIA AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct pci_device_id agp_via_pci_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VIA_GARTCTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VIA_APSIZE 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VIA_ATTBASE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VIA_AGP3_GARTCTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VIA_AGP3_APSIZE 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VIA_AGP3_ATTBASE 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIA_AGPSEL 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int via_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct aper_size_info_8 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int via_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* GART control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* attbase - aperture GATT base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void via_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct aper_size_info_8 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) previous_size = A_SIZE_8(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * during reinitialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void via_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) temp |= (1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) temp &= ~(1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct aper_size_info_8 via_generic_sizes[9] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {256, 65536, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {128, 32768, 5, 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {64, 16384, 4, 192},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {32, 8192, 3, 224},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {16, 4096, 2, 240},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {8, 2048, 1, 248},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {4, 1024, 0, 252},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {2, 512, 0, 254},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {1, 256, 0, 255}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int via_fetch_size_agp3(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct aper_size_info_16 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) temp &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int via_configure_agp3(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct aper_size_info_16 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) current_size = A_SIZE_16(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* attbase - aperture GATT base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) agp_bridge->gatt_bus_addr & 0xfffff000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * translation table first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * graphics AGP aperture for the AGP3.0 port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void via_cleanup_agp3(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct aper_size_info_16 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) previous_size = A_SIZE_16(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void via_tlbflush_agp3(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct agp_bridge_driver via_agp3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .aperture_sizes = agp3_generic_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num_aperture_sizes = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .configure = via_configure_agp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .fetch_size = via_fetch_size_agp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .cleanup = via_cleanup_agp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .tlb_flush = via_tlbflush_agp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .masks = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct agp_bridge_driver via_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .aperture_sizes = via_generic_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_aperture_sizes = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .configure = via_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .fetch_size = via_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .cleanup = via_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .tlb_flush = via_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .masks = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct agp_device_ids via_agp_device_ids[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .device_id = PCI_DEVICE_ID_VIA_82C597_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .chipset_name = "Apollo VP3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .device_id = PCI_DEVICE_ID_VIA_82C598_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .chipset_name = "Apollo MVP3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .device_id = PCI_DEVICE_ID_VIA_8501_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .chipset_name = "Apollo MVP4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* VT8601 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .device_id = PCI_DEVICE_ID_VIA_8601_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .chipset_name = "Apollo ProMedia/PLE133Ta",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* VT82C693A / VT28C694T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .device_id = PCI_DEVICE_ID_VIA_82C691_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .chipset_name = "Apollo Pro 133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .device_id = PCI_DEVICE_ID_VIA_8371_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .chipset_name = "KX133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* VT8633 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .device_id = PCI_DEVICE_ID_VIA_8633_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .chipset_name = "Pro 266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .device_id = PCI_DEVICE_ID_VIA_XN266,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .chipset_name = "Apollo Pro266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* VT8361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .device_id = PCI_DEVICE_ID_VIA_8361,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .chipset_name = "KLE133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* VT8365 / VT8362 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .device_id = PCI_DEVICE_ID_VIA_8363_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .chipset_name = "Twister-K/KT133x/KM133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* VT8753A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .device_id = PCI_DEVICE_ID_VIA_8753_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .chipset_name = "P4X266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* VT8366 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .device_id = PCI_DEVICE_ID_VIA_8367_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .chipset_name = "KT266/KY266x/KT333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* VT8633 (for CuMine/ Celeron) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .device_id = PCI_DEVICE_ID_VIA_8653_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .chipset_name = "Pro266T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* KM266 / PM266 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .device_id = PCI_DEVICE_ID_VIA_XM266,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .chipset_name = "PM266/KM266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* CLE266 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .device_id = PCI_DEVICE_ID_VIA_862X_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .chipset_name = "CLE266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .device_id = PCI_DEVICE_ID_VIA_8377_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .chipset_name = "KT400/KT400A/KT600",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* VT8604 / VT8605 / VT8603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * (Apollo Pro133A chipset with S3 Savage4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .device_id = PCI_DEVICE_ID_VIA_8605_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .chipset_name = "ProSavage PM133/PL133/PN133"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* P4M266x/P4N266 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .device_id = PCI_DEVICE_ID_VIA_8703_51_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .chipset_name = "P4M266x/P4N266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* VT8754 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .device_id = PCI_DEVICE_ID_VIA_8754C_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .chipset_name = "PT800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* P4X600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .device_id = PCI_DEVICE_ID_VIA_8763_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .chipset_name = "P4X600"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* KM400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .device_id = PCI_DEVICE_ID_VIA_8378_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .chipset_name = "KM400/KM400A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* PT880 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .device_id = PCI_DEVICE_ID_VIA_PT880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .chipset_name = "PT880",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* PT880 Ultra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .device_id = PCI_DEVICE_ID_VIA_PT880ULTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .chipset_name = "PT880 Ultra",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* PT890 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .device_id = PCI_DEVICE_ID_VIA_8783_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .chipset_name = "PT890",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* PM800/PN800/PM880/PN880 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .device_id = PCI_DEVICE_ID_VIA_PX8X0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .chipset_name = "PM800/PN800/PM880/PN880",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* KT880 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .device_id = PCI_DEVICE_ID_VIA_3269_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .chipset_name = "KT880",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* KTxxx/Px8xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .device_id = PCI_DEVICE_ID_VIA_83_87XX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* P4M800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .device_id = PCI_DEVICE_ID_VIA_3296_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .chipset_name = "P4M800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* P4M800CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .device_id = PCI_DEVICE_ID_VIA_P4M800CE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .chipset_name = "VT3314",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* VT3324 / CX700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .device_id = PCI_DEVICE_ID_VIA_VT3324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .chipset_name = "CX700",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * architecture, the AGP resource and behavior are different from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * the traditional AGP which resides only in chipset. AGP is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * by 3D driver which wasn't available for the VT3336 and VT3364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * generation until now. Unfortunately, by testing, VT3364 works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * but VT3336 doesn't. - explanation from via, just leave this as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * as a placeholder to avoid future patches adding it back in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .device_id = PCI_DEVICE_ID_VIA_VT3336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .chipset_name = "VT3336",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* P4M890 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .device_id = PCI_DEVICE_ID_VIA_P4M890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .chipset_name = "P4M890",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* P4M900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .device_id = PCI_DEVICE_ID_VIA_VT3364,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .chipset_name = "P4M900",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { }, /* dummy final entry, always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * with the same standards version as the graphics card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void check_via_agp3 (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Check AGP 2.0 compatibility mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((reg & (1<<1))==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bridge->driver = &via_agp3_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int agp_via_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct agp_device_ids *devs = via_agp_device_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) j = ent - agp_via_pci_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bridge->driver = &via_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Garg, there are KT400s with KT266 IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Is there a KT400 subsystem ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) check_via_agp3(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* If this is an AGP3 bridge, check which mode its in and adjust. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) get_agp_version(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (bridge->major_version >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) check_via_agp3(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void agp_via_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pci_save_state (pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_set_power_state (pdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int agp_via_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pci_set_power_state (pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (bridge->driver == &via_agp3_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return via_configure_agp3();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else if (bridge->driver == &via_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return via_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* must be the same order as name table above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct pci_device_id agp_via_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define ID(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .class = (PCI_CLASS_BRIDGE_HOST << 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .class_mask = ~0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .vendor = PCI_VENDOR_ID_VIA, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .device = x, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .subvendor = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ID(PCI_DEVICE_ID_VIA_82C597_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ID(PCI_DEVICE_ID_VIA_82C598_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ID(PCI_DEVICE_ID_VIA_8501_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ID(PCI_DEVICE_ID_VIA_8601_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ID(PCI_DEVICE_ID_VIA_82C691_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ID(PCI_DEVICE_ID_VIA_8371_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ID(PCI_DEVICE_ID_VIA_8633_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ID(PCI_DEVICE_ID_VIA_XN266),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ID(PCI_DEVICE_ID_VIA_8361),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ID(PCI_DEVICE_ID_VIA_8363_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ID(PCI_DEVICE_ID_VIA_8753_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ID(PCI_DEVICE_ID_VIA_8367_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ID(PCI_DEVICE_ID_VIA_8653_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ID(PCI_DEVICE_ID_VIA_XM266),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ID(PCI_DEVICE_ID_VIA_862X_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ID(PCI_DEVICE_ID_VIA_8377_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ID(PCI_DEVICE_ID_VIA_8605_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ID(PCI_DEVICE_ID_VIA_8703_51_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ID(PCI_DEVICE_ID_VIA_8754C_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ID(PCI_DEVICE_ID_VIA_8763_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ID(PCI_DEVICE_ID_VIA_8378_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ID(PCI_DEVICE_ID_VIA_PT880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ID(PCI_DEVICE_ID_VIA_8783_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ID(PCI_DEVICE_ID_VIA_PX8X0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ID(PCI_DEVICE_ID_VIA_3269_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ID(PCI_DEVICE_ID_VIA_83_87XX_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ID(PCI_DEVICE_ID_VIA_3296_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ID(PCI_DEVICE_ID_VIA_P4M800CE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ID(PCI_DEVICE_ID_VIA_VT3324),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ID(PCI_DEVICE_ID_VIA_P4M890),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ID(PCI_DEVICE_ID_VIA_VT3364),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct pci_driver agp_via_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "agpgart-via",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .id_table = agp_via_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .probe = agp_via_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .remove = agp_via_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .suspend = agp_via_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .resume = agp_via_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int __init agp_via_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return pci_register_driver(&agp_via_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void __exit agp_via_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pci_unregister_driver(&agp_via_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) module_init(agp_via_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) module_exit(agp_via_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_AUTHOR("Dave Jones");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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