^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UniNorth AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/uninorth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pmac_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NOTES for uninorth3 (G5 AGP) supports :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * There maybe also possibility to have bigger cache line size for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * agp (see pmac_pci.c and look for cache line). Need to be investigated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * by someone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * PAGE size are hardcoded but this may change, see asm/page.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Jerome Glisse <j.glisse@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int uninorth_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int is_u3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u32 scratch_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEFAULT_APERTURE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DEFAULT_APERTURE_STRING "256"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static char *aperture = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int uninorth_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int i, size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct aper_size_info_32 *values =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) A_SIZE_32(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (aperture) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) char *save = aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) size = memparse(aperture, &aperture) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) aperture = save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (size == values[i].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (i == agp_bridge->driver->num_aperture_sizes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "using default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) aperture = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (values[i].size == DEFAULT_APERTURE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) agp_bridge->current_size = (void *)(values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void uninorth_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 ctrl = UNI_N_CFG_GART_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (is_u3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ctrl |= U3_N_CFG_GART_PERFRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ctrl | UNI_N_CFG_GART_INVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!mem && uninorth_rev <= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ctrl | UNI_N_CFG_GART_2xRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void uninorth_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!(tmp & UNI_N_CFG_GART_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tmp |= UNI_N_CFG_GART_INVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (uninorth_rev <= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) UNI_N_CFG_GART_2xRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int uninorth_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct aper_size_info_32 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) current_size = A_SIZE_32(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* aperture size and gatt addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pci_write_config_dword(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) UNI_N_CFG_GART_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (agp_bridge->gatt_bus_addr & 0xfffff000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* HACK ALERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * UniNorth seem to be buggy enough not to handle properly when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * the AGP aperture isn't mapped at bus physical address 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) agp_bridge->gart_bus_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Assume U3 or later on PPC64 systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (agp_bridge->gatt_bus_addr >> 32) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pci_write_config_dword(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (is_u3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pci_write_config_dword(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) UNI_N_CFG_GART_DUMMY_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) page_to_phys(agp_bridge->scratch_page_page) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int i, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int mask_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (type != mem->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (mask_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* We know nothing of memory types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (mem->page_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) num_entries = A_SIZE_32(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((pg_start + mem->page_count) > num_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) gp = (u32 *) &agp_bridge->gatt_table[pg_start];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (i = 0; i < mem->page_count; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (gp[i] != scratch_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_info(&agp_bridge->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "uninorth_insert_memory: entry 0x%x occupied (%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i, gp[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for (i = 0; i < mem->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (is_u3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0x1UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uninorth_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int mask_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (type != mem->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (mask_type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* We know nothing of memory types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (mem->page_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) gp = (u32 *) &agp_bridge->gatt_table[pg_start];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < mem->page_count; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gp[i] = scratch_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uninorth_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 command, scratch, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_read_config_dword(bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bridge->capndx + PCI_AGP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) command = agp_collect_device_status(bridge, mode, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) command |= PCI_AGP_COMMAND_AGP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (uninorth_rev == 0x21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Darwin disable AGP 4x on this revision, thus we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * may assume it's broken. This is an AGP2 controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) command &= ~AGPSTAT2_4X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * 2.2 and 2.3, Darwin do so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) command = (command & ~AGPSTAT_RQ_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) | (7 << AGPSTAT_RQ_DEPTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uninorth_tlbflush(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pci_write_config_dword(bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bridge->capndx + PCI_AGP_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pci_read_config_dword(bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bridge->capndx + PCI_AGP_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "command register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (uninorth_rev >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* This is an AGP V3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* AGP V2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) agp_device_command(command, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uninorth_tlbflush(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * These Power Management routines are _not_ called by the normal PCI PM layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * but directly by the video driver through function pointers in the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int agp_uninorth_suspend(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 agp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct pci_dev *device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bridge = agp_find_bridge(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (bridge == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Only one suspend supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (bridge->dev_private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* turn off AGP on the video chip, if it was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for_each_pci_dev(device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Don't touch the bridge yet, device first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (device == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Only deal with devices on the same bus here, no Mac has a P2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * bridge on the AGP port, and mucking around the entire PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * tree is source of problems on some machines because of a bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * in some versions of pci_find_capability() when hitting a dead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (device->bus != pdev->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) agp = pci_find_capability(device, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!agp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!(cmd & PCI_AGP_COMMAND_AGP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_info(&pdev->dev, "disabling AGP on device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pci_name(device));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmd &= ~PCI_AGP_COMMAND_AGP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* turn off AGP on the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bridge->dev_private_data = (void *)(long)cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (cmd & PCI_AGP_COMMAND_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_info(&pdev->dev, "disabling AGP on bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cmd &= ~PCI_AGP_COMMAND_AGP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* turn off the GART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uninorth_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int agp_uninorth_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bridge = agp_find_bridge(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (bridge == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) command = (long)bridge->dev_private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bridge->dev_private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!(command & PCI_AGP_COMMAND_AGP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uninorth_agp_enable(bridge, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct page **pages_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } uninorth_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) char *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) char *table_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* We can't handle 2 level gatt's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (bridge->driver->size_type == LVL2_APER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) i = bridge->aperture_size_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) temp = bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) size = page_order = num_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) size = A_SIZE_32(temp)->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) page_order = A_SIZE_32(temp)->page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) num_entries = A_SIZE_32(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) table = (char *) __get_free_pages(GFP_KERNEL, page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (table == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) bridge->current_size = A_IDX32(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } while (!table && (i < bridge->driver->num_aperture_sizes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (table == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uninorth_priv.pages_arr = kmalloc_array(1 << page_order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sizeof(struct page *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (uninorth_priv.pages_arr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) goto enomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) page++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SetPageReserved(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uninorth_priv.pages_arr[i] = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bridge->gatt_table_real = (u32 *) table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Need to clear out any dirty data still sitting in caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) flush_dcache_range((unsigned long)table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (unsigned long)table_end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) bridge->gatt_table = vmap(uninorth_priv.pages_arr, (1 << page_order), 0, PAGE_KERNEL_NCG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (bridge->gatt_table == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto enomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bridge->gatt_bus_addr = virt_to_phys(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (is_u3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) scratch_value = (page_to_phys(agp_bridge->scratch_page_page) >> PAGE_SHIFT) | 0x80000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) scratch_value = cpu_to_le32((page_to_phys(agp_bridge->scratch_page_page) & 0xFFFFF000UL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x1UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for (i = 0; i < num_entries; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bridge->gatt_table[i] = scratch_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) enomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) kfree(uninorth_priv.pages_arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) free_pages((unsigned long)table, page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) char *table, *table_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) temp = bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) page_order = A_SIZE_32(temp)->page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Do not worry about freeing memory, because if this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * called, then all agp memory is deallocated and removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * from the table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) vunmap(bridge->gatt_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) kfree(uninorth_priv.pages_arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) table = (char *) bridge->gatt_table_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ClearPageReserved(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) free_pages((unsigned long) bridge->gatt_table_real, page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void null_cache_flush(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Setup function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct aper_size_info_32 uninorth_sizes[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {256, 65536, 6, 64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {128, 32768, 5, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {64, 16384, 4, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {32, 8192, 3, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {16, 4096, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {8, 2048, 1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {4, 1024, 0, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * Not sure that u3 supports that high aperture sizes but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * would strange if it did not :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct aper_size_info_32 u3_sizes[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {512, 131072, 7, 128},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {256, 65536, 6, 64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {128, 32768, 5, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {64, 16384, 4, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {32, 8192, 3, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {16, 4096, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {8, 2048, 1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {4, 1024, 0, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) const struct agp_bridge_driver uninorth_agp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .aperture_sizes = (void *)uninorth_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .size_type = U32_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .configure = uninorth_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .fetch_size = uninorth_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .cleanup = uninorth_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .tlb_flush = uninorth_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .masks = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .cache_flush = null_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .agp_enable = uninorth_agp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .create_gatt_table = uninorth_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .free_gatt_table = uninorth_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .insert_memory = uninorth_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .remove_memory = uninorth_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .cant_use_aperture = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) const struct agp_bridge_driver u3_agp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .aperture_sizes = (void *)u3_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .size_type = U32_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .num_aperture_sizes = ARRAY_SIZE(u3_sizes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .configure = uninorth_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .fetch_size = uninorth_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .cleanup = uninorth_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .tlb_flush = uninorth_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .masks = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .cache_flush = null_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .agp_enable = uninorth_agp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .create_gatt_table = uninorth_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .free_gatt_table = uninorth_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .insert_memory = uninorth_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .remove_memory = uninorth_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .cant_use_aperture = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct agp_device_ids uninorth_agp_device_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .chipset_name = "UniNorth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .chipset_name = "UniNorth/Pangea",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .chipset_name = "UniNorth 1.5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .chipset_name = "UniNorth 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .chipset_name = "U3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .chipset_name = "U3L",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .chipset_name = "U3H",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .chipset_name = "UniNorth/Intrepid2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int agp_uninorth_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct agp_device_ids *devs = uninorth_agp_device_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct device_node *uninorth_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (cap_ptr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* probe for known chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) for (j = 0; devs[j].chipset_name != NULL; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (pdev->device == devs[j].device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_info(&pdev->dev, "Apple %s chipset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) devs[j].chipset_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pdev->vendor, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Set revision to 0 if we could not read it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) uninorth_rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) is_u3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Locate core99 Uni-N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uninorth_node = of_find_node_by_name(NULL, "uni-n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Locate G5 u3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (uninorth_node == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) is_u3 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) uninorth_node = of_find_node_by_name(NULL, "u3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (uninorth_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) const int *revprop = of_get_property(uninorth_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "device-rev", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (revprop != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uninorth_rev = *revprop & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) of_node_put(uninorth_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Inform platform of our suspend/resume caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Allocate & setup our driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (is_u3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bridge->driver = &u3_agp_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) bridge->driver = &uninorth_agp_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bridge->flags = AGP_ERRATA_FASTWRITES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void agp_uninorth_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Inform platform of our suspend/resume caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) pmac_register_agp_pm(pdev, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct pci_device_id agp_uninorth_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .vendor = PCI_VENDOR_ID_APPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .device = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct pci_driver agp_uninorth_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .name = "agpgart-uninorth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .id_table = agp_uninorth_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .probe = agp_uninorth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .remove = agp_uninorth_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int __init agp_uninorth_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return pci_register_driver(&agp_uninorth_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void __exit agp_uninorth_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pci_unregister_driver(&agp_uninorth_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) module_init(agp_uninorth_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) module_exit(agp_uninorth_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) module_param(aperture, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MODULE_PARM_DESC(aperture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "Aperture size, must be power of two between 4MB and an\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "\t\tupper limit specific to the UniNorth revision.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "\t\tDefault: " DEFAULT_APERTURE_STRING "M");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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