^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Serverworks AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SVWRKS_COMMAND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SVWRKS_APSIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SVWRKS_MMBASE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SVWRKS_CACHING 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SVWRKS_AGP_ENABLE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SVWRKS_FEATURE 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SVWRKS_SIZE_MASK 0xfe000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Memory mapped registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SVWRKS_GART_CACHE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SVWRKS_GATTBASE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SVWRKS_TLBFLUSH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SVWRKS_POSTFLUSH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SVWRKS_DIRFLUSH 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct serverworks_page_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long *real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long __iomem *remapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct _serverworks_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pci_dev *svrwrks_dev; /* device one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) volatile u8 __iomem *registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct serverworks_page_map **gatt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int num_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct serverworks_page_map scratch_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int gart_addr_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int mm_addr_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } serverworks_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int serverworks_create_page_map(struct serverworks_page_map *page_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (page_map->real == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) set_memory_uc((unsigned long)page_map->real, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) page_map->remapped = page_map->real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel(agp_bridge->scratch_page, page_map->remapped+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Red Pen: Everyone else does pci posting flush here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void serverworks_free_page_map(struct serverworks_page_map *page_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) set_memory_wb((unsigned long)page_map->real, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) free_page((unsigned long) page_map->real);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void serverworks_free_gatt_pages(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct serverworks_page_map **tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct serverworks_page_map *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tables = serverworks_private.gatt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (i = 0; i < serverworks_private.num_tables; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) entry = tables[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (entry != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (entry->real != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) serverworks_free_page_map(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) kfree(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) kfree(tables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int serverworks_create_gatt_pages(int nr_tables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct serverworks_page_map **tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct serverworks_page_map *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tables = kcalloc(nr_tables + 1, sizeof(struct serverworks_page_map *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (tables == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for (i = 0; i < nr_tables; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (entry == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tables[i] = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) retval = serverworks_create_page_map(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (retval != 0) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) serverworks_private.num_tables = nr_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) serverworks_private.gatt_pages = tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (retval != 0) serverworks_free_gatt_pages();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GET_PAGE_DIR_IDX(addr)]->remapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifndef GET_PAGE_DIR_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifndef GET_PAGE_DIR_IDX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifndef GET_GATT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct aper_size_info_lvl2 *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct serverworks_page_map page_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) value = A_SIZE_LVL2(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) retval = serverworks_create_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) serverworks_free_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Create a fake scratch directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < 1024; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) retval = serverworks_create_gatt_pages(value->num_entries / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) serverworks_free_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) serverworks_free_page_map(&serverworks_private.scratch_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) agp_bridge->gatt_table_real = (u32 *)page_dir.real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Get the address for the gart region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * This is a bus address even on the alpha, b/c its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * used to program the agp master not the cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Calculate the agp offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (i = 0; i < value->num_entries / 1024; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct serverworks_page_map page_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) serverworks_free_gatt_pages();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) serverworks_free_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) serverworks_free_page_map(&serverworks_private.scratch_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int serverworks_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct aper_size_info_lvl2 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SVWRKS_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) temp2 &= SVWRKS_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (temp2 == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * This routine could be implemented by taking the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * written to the GATT, and flushing them individually. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * currently it just flushes the whole table. Which is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * more efficient, since agp_memory blocks can be a large number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void serverworks_tlbflush(struct agp_memory *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) timeout = jiffies + 3*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(&serverworks_private.svrwrks_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "TLB post flush took more than 3 seconds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) timeout = jiffies + 3*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(&serverworks_private.svrwrks_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "TLB Dir flush took more than 3 seconds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int serverworks_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct aper_size_info_lvl2 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 cap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) current_size = A_SIZE_LVL2(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Get the memory mapped registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!serverworks_private.registers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(&agp_bridge->dev->dev, "can't ioremap(%#x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cap_reg &= ~0x0007;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cap_reg |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) readw(serverworks_private.registers+SVWRKS_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) enable_reg |= 0x1; /* Agp Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) serverworks_tlbflush(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pci_read_config_dword(serverworks_private.svrwrks_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enable_reg &= ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) enable_reg |= (1<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void serverworks_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iounmap((void __iomem *) serverworks_private.registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int serverworks_insert_memory(struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i, j, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long __iomem *cur_gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (type != 0 || mem->type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if ((pg_start + mem->page_count) > num_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) j = pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) while (j < (pg_start + mem->page_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cur_gatt = SVRWRKS_GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cur_gatt = SVRWRKS_GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writel(agp_bridge->driver->mask_memory(agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) page_to_phys(mem->pages[i]), mem->type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cur_gatt+GET_GATT_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) serverworks_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long __iomem *cur_gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (type != 0 || mem->type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) serverworks_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = pg_start; i < (mem->page_count + pg_start); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cur_gatt = SVRWRKS_GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) serverworks_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct gatt_mask serverworks_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {.mask = 1, .type = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct aper_size_info_lvl2 serverworks_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {2048, 524288, 0x80000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {1024, 262144, 0xc0000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {512, 131072, 0xe0000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {256, 65536, 0xf0000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {128, 32768, 0xf8000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {64, 16384, 0xfc000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {32, 8192, 0xfe000000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pci_read_config_dword(serverworks_private.svrwrks_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) bridge->capndx + PCI_AGP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) command = agp_collect_device_status(bridge, mode, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) command &= ~0x10; /* disable FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) command &= ~0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) command |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_write_config_dword(serverworks_private.svrwrks_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bridge->capndx + PCI_AGP_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) agp_device_command(command, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct agp_bridge_driver sworks_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .aperture_sizes = serverworks_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .size_type = LVL2_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .configure = serverworks_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .fetch_size = serverworks_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .cleanup = serverworks_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .tlb_flush = serverworks_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .masks = serverworks_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .agp_enable = serverworks_agp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .create_gatt_table = serverworks_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .free_gatt_table = serverworks_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .insert_memory = serverworks_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .remove_memory = serverworks_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int agp_serverworks_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct pci_dev *bridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 temp, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 cap_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 0x0006:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&pdev->dev, "ServerWorks CNB20HE is unsupported due to lack of documentation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case PCI_DEVICE_ID_SERVERWORKS_HE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case PCI_DEVICE_ID_SERVERWORKS_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 0x0007:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(&pdev->dev, "unsupported Serverworks chipset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "[%04x/%04x]\n", pdev->vendor, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Everything is on func 1 here so we are hardcoding function one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (unsigned int)pdev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PCI_DEVFN(0, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!bridge_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_info(&pdev->dev, "can't find secondary device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) serverworks_private.svrwrks_dev = bridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) serverworks_private.gart_addr_ofs = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (temp2 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_info(&pdev->dev, "64 bit aperture address, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "but top bits are not zero; disabling AGP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) serverworks_private.mm_addr_ofs = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) serverworks_private.mm_addr_ofs = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) serverworks_private.mm_addr_ofs + 4, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (temp2 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_info(&pdev->dev, "64 bit MMIO address, but top "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "bits are not zero; disabling AGP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bridge->driver = &sworks_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bridge->dev_private_data = &serverworks_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bridge->dev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void agp_serverworks_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pci_dev_put(bridge->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pci_dev_put(serverworks_private.svrwrks_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) serverworks_private.svrwrks_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct pci_device_id agp_serverworks_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .vendor = PCI_VENDOR_ID_SERVERWORKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .device = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct pci_driver agp_serverworks_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "agpgart-serverworks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .id_table = agp_serverworks_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .probe = agp_serverworks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .remove = agp_serverworks_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int __init agp_serverworks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return pci_register_driver(&agp_serverworks_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void __exit agp_serverworks_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pci_unregister_driver(&agp_serverworks_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) module_init(agp_serverworks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) module_exit(agp_serverworks_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL and additional rights");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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