Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * SiS AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define SIS_ATTBASE	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SIS_APSIZE	0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SIS_TLBCNTRL	0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define SIS_TLBFLUSH	0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PCI_DEVICE_ID_SI_662	0x0662
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PCI_DEVICE_ID_SI_671	0x0671
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static bool agp_sis_force_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int agp_sis_agp_spec = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static int sis_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 temp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct aper_size_info_8 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		if ((temp_size == values[i].size_value) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		    ((temp_size & ~(0x07)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		     (values[i].size_value & ~(0x07)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			    agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void sis_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int sis_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 						    AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			       agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			      current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void sis_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct aper_size_info_8 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	previous_size = A_SIZE_8(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			      (previous_size->size_value & ~(0x03)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct pci_dev *device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dev_info(&agp_bridge->dev->dev, "AGP %d.%d bridge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 agp_bridge->major_version, agp_bridge->minor_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	command = agp_collect_device_status(bridge, mode, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	command |= AGPSTAT_AGP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rate = (command & 0x7) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	for_each_pci_dev(device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (!agp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_info(&agp_bridge->dev->dev, "putting AGP V3 device at %s into %dx mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			 pci_name(device), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		 * Weird: on some sis chipsets any rate change in the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 * command register triggers a 5ms screwup during which the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 * cannot be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (device->device == bridge->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			dev_info(&agp_bridge->dev->dev, "SiS delay workaround: giving bridge time to recover\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct aper_size_info_8 sis_generic_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{256, 65536, 6, 99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{128, 32768, 5, 83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{64, 16384, 4, 67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{32, 8192, 3, 51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{16, 4096, 2, 35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{8, 2048, 1, 19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{4, 1024, 0, 3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct agp_bridge_driver sis_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.aperture_sizes		= sis_generic_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.size_type		= U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.num_aperture_sizes	= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.needs_scratch_page	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.configure		= sis_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.fetch_size		= sis_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.cleanup		= sis_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.tlb_flush		= sis_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.mask_memory		= agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.masks			= NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.agp_enable		= agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.cache_flush		= global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.create_gatt_table	= agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.free_gatt_table	= agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.insert_memory		= agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.remove_memory		= agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.alloc_by_type		= agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.free_by_type		= agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.agp_alloc_page		= agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.agp_alloc_pages	= agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.agp_destroy_page	= agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.agp_destroy_pages	= agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) // chipsets that require the 'delay hack'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int sis_broken_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PCI_DEVICE_ID_SI_648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PCI_DEVICE_ID_SI_746,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	0 // terminator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void sis_get_driver(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for (i=0; sis_broken_chipsets[i]!=0; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (bridge->dev->device==sis_broken_chipsets[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (sis_broken_chipsets[i] || agp_sis_force_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		sis_driver.agp_enable=sis_delayed_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	// sis chipsets that indicate less than agp3.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	// are not actually fully agp3 compliant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	     && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		sis_driver.aperture_sizes = agp3_generic_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		sis_driver.size_type = U16_APER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		sis_driver.configure = agp3_generic_configure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		sis_driver.fetch_size = agp3_generic_fetch_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		sis_driver.cleanup = agp3_generic_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		sis_driver.tlb_flush = agp3_generic_tlbflush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int agp_sis_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	dev_info(&pdev->dev, "SiS chipset [%04x/%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 pdev->vendor, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bridge->driver = &sis_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	get_agp_version(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	sis_get_driver(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void agp_sis_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int agp_sis_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int agp_sis_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return sis_driver.configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct pci_device_id agp_sis_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.device		= PCI_DEVICE_ID_SI_5591,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.device		= PCI_DEVICE_ID_SI_530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.device		= PCI_DEVICE_ID_SI_540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.device		= PCI_DEVICE_ID_SI_550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.device		= PCI_DEVICE_ID_SI_620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.device		= PCI_DEVICE_ID_SI_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.device		= PCI_DEVICE_ID_SI_635,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.device		= PCI_DEVICE_ID_SI_645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.device		= PCI_DEVICE_ID_SI_646,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.device		= PCI_DEVICE_ID_SI_648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.device		= PCI_DEVICE_ID_SI_650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.device		= PCI_DEVICE_ID_SI_651,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.device		= PCI_DEVICE_ID_SI_655,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.device		= PCI_DEVICE_ID_SI_661,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.device		= PCI_DEVICE_ID_SI_662,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.device		= PCI_DEVICE_ID_SI_671,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.device		= PCI_DEVICE_ID_SI_730,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.device		= PCI_DEVICE_ID_SI_735,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		.device		= PCI_DEVICE_ID_SI_740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.device		= PCI_DEVICE_ID_SI_741,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.device		= PCI_DEVICE_ID_SI_745,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.vendor		= PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		.device		= PCI_DEVICE_ID_SI_746,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct pci_driver agp_sis_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.name		= "agpgart-sis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.id_table	= agp_sis_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.probe		= agp_sis_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.remove		= agp_sis_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	.suspend	= agp_sis_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.resume		= agp_sis_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int __init agp_sis_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return pci_register_driver(&agp_sis_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void __exit agp_sis_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	pci_unregister_driver(&agp_sis_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_init(agp_sis_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) module_exit(agp_sis_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) module_param(agp_sis_force_delay, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) module_param(agp_sis_agp_spec, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_LICENSE("GPL and additional rights");