Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * HP Quicksilver AGP GART routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on drivers/char/agpgart/hp-agp.c which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/klist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/ropes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRVNAME	"quicksilver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DRVPFX	DRVNAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AGP8X_MODE_BIT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AGP8X_MODE		(1 << AGP8X_MODE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		       int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct _parisc_agp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void __iomem *ioc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *lba_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int lba_cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u64 *gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u64 gatt_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u64 gart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u64 gart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int io_pages_per_kpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) } parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct gatt_mask parisc_agp_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)         {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.mask = SBA_PDIR_VALID_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.type = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct aper_size_info_fixed parisc_agp_sizes[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)         {0, 0, 0},              /* filled in by parisc_agp_fetch_size() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) parisc_agp_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	size = parisc_agp_info.gart_size / MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	parisc_agp_sizes[0].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	agp_bridge->current_size = (void *) &parisc_agp_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) parisc_agp_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	agp_bridge->gart_bus_addr = info->gart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	agp_bridge->capndx = info->lba_cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) parisc_agp_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	readq(info->ioc_regs+IOC_PCOM);	/* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	for (i = 0; i < info->gatt_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	info->gatt[0] = SBA_AGPGART_COOKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	off_t j, io_pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int io_pg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	io_pg_start = info->io_pages_per_kpage * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	io_pg_count = info->io_pages_per_kpage * mem->page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if ((io_pg_start + io_pg_count) > info->gatt_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	j = io_pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	while (j < (io_pg_start + io_pg_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (info->gatt[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		paddr = page_to_phys(mem->pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		for (k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		     k < info->io_pages_per_kpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		     k++, j++, paddr += info->io_page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			info->gatt[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				parisc_agp_mask_memory(agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					paddr, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int i, io_pg_start, io_pg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	io_pg_start = info->io_pages_per_kpage * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	io_pg_count = info->io_pages_per_kpage * mem->page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		info->gatt[i] = agp_bridge->scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		       int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return SBA_PDIR_VALID_BIT | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	command = agp_collect_device_status(bridge, mode, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	command |= 0x00000100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	agp_device_command(command, (mode & AGP8X_MODE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct agp_bridge_driver parisc_agp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.size_type		= FIXED_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.configure		= parisc_agp_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.fetch_size		= parisc_agp_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.tlb_flush		= parisc_agp_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.mask_memory		= parisc_agp_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.masks			= parisc_agp_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.agp_enable		= parisc_agp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.cache_flush		= global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.create_gatt_table	= parisc_agp_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.free_gatt_table	= parisc_agp_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.insert_memory		= parisc_agp_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.remove_memory		= parisc_agp_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.alloc_by_type		= agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.free_by_type		= agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.agp_alloc_page		= agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.agp_alloc_pages	= agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.agp_destroy_page	= agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.agp_destroy_pages	= agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.cant_use_aperture	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) agp_ioc_init(void __iomem *ioc_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)         u64 iova_base, *io_pdir, io_tlb_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)         int io_tlb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)         printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)         info->ioc_regs = ioc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)         io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)         switch (io_tlb_ps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)         case 0: io_tlb_shift = 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)         case 1: io_tlb_shift = 13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)         case 2: io_tlb_shift = 14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)         case 3: io_tlb_shift = 16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)         default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)                 printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)                        "configuration 0x%llx\n", io_tlb_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)                 info->gatt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)                 info->gatt_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)                 return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)         info->io_page_size = 1 << io_tlb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)         info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)         iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)         info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)         info->gart_size = PLUTO_GART_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)         info->gatt_entries = info->gart_size / info->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)         io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)         info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)         if (info->gatt[0] != SBA_AGPGART_COOKIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)                 info->gatt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)                 info->gatt_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)                 printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)                        "GART disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)                 return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)         return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) lba_find_capability(int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)         u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)         u8 pos, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)         int ttl = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)         status = readw(info->lba_regs + PCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)         if (!(status & PCI_STATUS_CAP_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)                 return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)         pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)         while (ttl-- && pos >= 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)                 pos &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)                 id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)                 if (id == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)                         break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)                 if (id == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)                         return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)                 pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)         return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) agp_lba_init(void __iomem *lba_hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct _parisc_agp_info *info = &parisc_agp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)         int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	info->lba_regs = lba_hpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)         info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)         cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)         if (cap != PCI_CAP_ID_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)                 printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)                        cap, info->lba_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)                 return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)         return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct pci_dev *fake_bridge_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	fake_bridge_dev = pci_alloc_dev(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (!fake_bridge_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	error = agp_ioc_init(ioc_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	error = agp_lba_init(lba_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (!bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	bridge->driver = &parisc_agp_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	bridge->dev = fake_bridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	error = agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	kfree(fake_bridge_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) find_quicksilver(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	struct parisc_device **lba = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct parisc_device *padev = to_parisc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (IS_QUICKSILVER(padev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		*lba = padev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) parisc_agp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	extern struct sba_device *sba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	int err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct parisc_device *sba = NULL, *lba = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct lba_device *lbadev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!sba_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/* Find our parent Pluto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	sba = sba_list->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (!IS_PLUTO(sba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	/* Now search our Pluto for our precious AGP device... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	device_for_each_child(&sba->dev, &lba, find_quicksilver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (!lba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		printk(KERN_INFO DRVPFX "No AGP devices found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	lbadev = parisc_get_drvdata(lba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	/* w00t, let's go find our cookies... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) module_init(parisc_agp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_LICENSE("GPL");