Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Common Intel AGPGART and GTT definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _INTEL_AGP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _INTEL_AGP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* Intel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define INTEL_APSIZE	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define INTEL_ATTBASE	0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define INTEL_AGPCTRL	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define INTEL_NBXCFG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define INTEL_ERRSTS	0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Intel i830 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define I830_GMCH_CTRL			0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define I830_GMCH_ENABLED		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define I830_GMCH_MEM_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define I830_GMCH_MEM_64M		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define I830_GMCH_MEM_128M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define I830_GMCH_GMS_MASK		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define I830_GMCH_GMS_DISABLED		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define I830_GMCH_GMS_LOCAL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define I830_GMCH_GMS_STOLEN_512	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define I830_GMCH_GMS_STOLEN_1024	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define I830_GMCH_GMS_STOLEN_8192	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define I830_RDRAM_CHANNEL_TYPE		0x03010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define I830_RDRAM_ND(x)		(((x) & 0x20) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define I830_RDRAM_DDT(x)		(((x) & 0x18) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* This one is for I830MP w. an external graphic card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define INTEL_I830_ERRSTS	0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* Intel 855GM/852GM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define I855_GMCH_GMS_MASK		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define I855_GMCH_GMS_STOLEN_0M		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define I855_GMCH_GMS_STOLEN_1M		(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define I855_GMCH_GMS_STOLEN_4M		(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define I855_GMCH_GMS_STOLEN_8M		(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define I855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define I855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define I85X_CAPID			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define I85X_VARIANT_MASK		0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define I85X_VARIANT_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define I855_GME			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define I855_GM				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define I852_GME			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define I852_GM				0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Intel i845 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define INTEL_I845_AGPM		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define INTEL_I845_ERRSTS	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Intel i860 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define INTEL_I860_MCHCFG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define INTEL_I860_ERRSTS	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Intel i810 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define I810_GMADR_BAR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define I810_MMADR_BAR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define I810_PTE_BASE		0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define I810_PTE_MAIN_UNCACHED	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define I810_PTE_LOCAL		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define I810_PTE_VALID		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define I830_PTE_SYSTEM_CACHED  0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define I810_SMRAM_MISCC	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define I810_GFX_MEM_WIN_SIZE	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define I810_GFX_MEM_WIN_32M	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define I810_GMS		0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define I810_GMS_DISABLE	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define I810_PGETBL_CTL		0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define I810_PGETBL_ENABLED	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Note: PGETBL_CTL2 has a different offset on G33. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define I965_PGETBL_CTL2	0x20c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define I965_PGETBL_SIZE_MASK	0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define I965_PGETBL_SIZE_512KB	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define I965_PGETBL_SIZE_256KB	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define I965_PGETBL_SIZE_128KB	(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define I965_PGETBL_SIZE_1MB	(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define I965_PGETBL_SIZE_2MB	(4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define I965_PGETBL_SIZE_1_5MB	(5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define G33_GMCH_SIZE_MASK	(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define G33_GMCH_SIZE_1M	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define G33_GMCH_SIZE_2M	(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define G4x_GMCH_SIZE_MASK	(0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define G4x_GMCH_SIZE_1M	(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define G4x_GMCH_SIZE_2M	(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define G4x_GMCH_SIZE_VT_EN	(0x8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define G4x_GMCH_SIZE_VT_1M	(G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define G4x_GMCH_SIZE_VT_1_5M	((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GFX_FLSH_CNTL		0x2170 /* 915+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define I810_DRAM_CTL		0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define I810_DRAM_ROW_0		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define I810_DRAM_ROW_0_SDRAM	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Intel 815 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INTEL_815_APCONT	0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INTEL_815_ATTBASE_MASK	~0x1FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Intel i820 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INTEL_I820_RDCR		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INTEL_I820_ERRSTS	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Intel i840 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INTEL_I840_MCHCFG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INTEL_I840_ERRSTS	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Intel i850 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define INTEL_I850_MCHCFG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define INTEL_I850_ERRSTS	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* intel 915G registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define I915_GMADR_BAR	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I915_MMADR_BAR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I915_PTE_BAR	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define I915_GMCH_GMS_STOLEN_48M	(0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define I915_GMCH_GMS_STOLEN_64M	(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define G33_GMCH_GMS_STOLEN_128M	(0x8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define G33_GMCH_GMS_STOLEN_256M	(0x9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INTEL_GMCH_GMS_STOLEN_96M	(0xa << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INTEL_GMCH_GMS_STOLEN_160M	(0xb << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INTEL_GMCH_GMS_STOLEN_224M	(0xc << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define I915_IFPADDR    0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define I830_HIC        0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Intel 965G registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I965_MSAC 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I965_IFPADDR    0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Intel 7505 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define INTEL_I7505_APSIZE	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define INTEL_I7505_NCAPID	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define INTEL_I7505_NISTAT	0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define INTEL_I7505_ATTBASE	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INTEL_I7505_ERRSTS	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define INTEL_I7505_AGPCTRL	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define INTEL_I7505_MCHCFG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* pci devices ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCI_DEVICE_ID_INTEL_E7221_HB	0x2588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCI_DEVICE_ID_INTEL_E7221_IG	0x258a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB        0xA010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG        0xA011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB         0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG         0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCI_DEVICE_ID_INTEL_B43_1_HB        0x2E90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCI_DEVICE_ID_INTEL_B43_1_IG        0x2E92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB        0x2E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG        0x2E02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB	    0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB	    0x0069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG	    0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB	    0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif