^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Intel AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "intel-agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/intel-gtt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int intel_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct aper_size_info_16 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int __intel_8xx_fetch_size(u8 temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct aper_size_info_8 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int intel_8xx_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return __intel_8xx_fetch_size(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int intel_815_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Intel 815 chipsets have a _weird_ APSIZE register with only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * one non-reserved bit, so mask the others out ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) temp &= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return __intel_8xx_fetch_size(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void intel_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void intel_8xx_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void intel_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct aper_size_info_16 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) previous_size = A_SIZE_16(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void intel_8xx_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct aper_size_info_8 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) previous_size = A_SIZE_8(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int intel_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct aper_size_info_16 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) current_size = A_SIZE_16(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* paccfg/nbxcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (temp2 & ~(1 << 10)) | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* clear any possible error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int intel_815_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* the Intel 815 chipset spec. says that bits 29-31 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * ATTBASE register are reserved -> try not to write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) addr &= INTEL_815_ATTBASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) addr |= agp_bridge->gatt_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* apcont */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* clear any possible error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Oddness : this chipset seems to have no ERRSTS register ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void intel_820_tlbflush(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void intel_820_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct aper_size_info_8 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) previous_size = A_SIZE_8(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) temp & ~(1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int intel_820_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* global enable aperture access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* This flag is not accessed through MCHCFG register as in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* i850 chipset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* clear any possible AGP-related error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int intel_840_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* mcgcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* clear any possible error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int intel_845_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (agp_bridge->apbase_config != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) agp_bridge->apbase_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) agp_bridge->apbase_config = agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* agpm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* clear any possible error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int intel_850_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* mcgcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* clear any possible AGP-related error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int intel_860_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* mcgcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* clear any possible AGP-related error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int intel_830mp_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* gmch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* clear any possible AGP-related error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int intel_7505_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* attbase - aperture base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* mchcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Setup function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct gatt_mask intel_generic_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {.mask = 0x00000017, .type = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct aper_size_info_8 intel_815_sizes[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {64, 16384, 4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {32, 8192, 3, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct aper_size_info_8 intel_8xx_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {256, 65536, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {128, 32768, 5, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {64, 16384, 4, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {32, 8192, 3, 56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {16, 4096, 2, 60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {8, 2048, 1, 62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {4, 1024, 0, 63}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct aper_size_info_16 intel_generic_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {256, 65536, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {128, 32768, 5, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {64, 16384, 4, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {32, 8192, 3, 56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {16, 4096, 2, 60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {8, 2048, 1, 62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {4, 1024, 0, 63}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct aper_size_info_8 intel_830mp_sizes[4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {256, 65536, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {128, 32768, 5, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {64, 16384, 4, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {32, 8192, 3, 56}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct agp_bridge_driver intel_generic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .aperture_sizes = intel_generic_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .size_type = U16_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .configure = intel_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .fetch_size = intel_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .cleanup = intel_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .tlb_flush = intel_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct agp_bridge_driver intel_815_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .aperture_sizes = intel_815_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_aperture_sizes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .configure = intel_815_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .fetch_size = intel_815_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct agp_bridge_driver intel_820_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .configure = intel_820_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .cleanup = intel_820_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .tlb_flush = intel_820_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct agp_bridge_driver intel_830mp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .aperture_sizes = intel_830mp_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .num_aperture_sizes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .configure = intel_830mp_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct agp_bridge_driver intel_840_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .configure = intel_840_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct agp_bridge_driver intel_845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .configure = intel_845_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct agp_bridge_driver intel_850_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .configure = intel_850_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct agp_bridge_driver intel_860_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .configure = intel_860_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct agp_bridge_driver intel_7505_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .aperture_sizes = intel_8xx_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .configure = intel_7505_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .fetch_size = intel_8xx_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .cleanup = intel_8xx_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .tlb_flush = intel_8xx_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .masks = intel_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .insert_memory = agp_generic_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * driver and gmch_driver must be non-null, and find_gmch will determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * which one should be used if a gmch_chip_id is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct intel_agp_driver_description {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) const struct agp_bridge_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } intel_agp_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { PCI_DEVICE_ID_INTEL_82845_HB, "i845", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { PCI_DEVICE_ID_INTEL_82845G_HB, "845G", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { 0, NULL, NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int agp_intel_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 cap_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (intel_gmch_probe(pdev, NULL, bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto found_gmch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* In case that multiple models of gfx chip may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) stand on same host bridge type, this can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) sure we detect the right IGD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (pdev->device == intel_agp_chipsets[i].chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bridge->driver = intel_agp_chipsets[i].driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!bridge->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pdev->vendor, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) bridge->dev_private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * The following fixes the case where the BIOS has "forgotten" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * provide an address range for the GART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * 20030610 - hamish@zot.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * This happens before pci_enable_device() intentionally;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * calling pci_enable_device() before assigning the resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * will result in the GART being disabled on machines with such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * BIOSs (the GART ends up with a BAR starting at 0, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * conflicts a lot of other devices).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) r = &pdev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!r->start && r->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (pci_assign_resource(pdev, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_err(&pdev->dev, "can't assign resource 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * If the device has not been properly setup, the following will catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * the problem and should stop the system from crashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * 20030610 - hamish@zot.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(&pdev->dev, "can't enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (cap_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) bridge->capndx+PCI_AGP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) found_gmch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) err = agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void agp_intel_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) intel_gmch_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int agp_intel_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) bridge->driver->configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct pci_device_id agp_intel_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define ID(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .class = (PCI_CLASS_BRIDGE_HOST << 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .class_mask = ~0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .vendor = PCI_VENDOR_ID_INTEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .device = x, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .subvendor = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ID(PCI_DEVICE_ID_INTEL_82441), /* for HAS2 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ID(PCI_DEVICE_ID_INTEL_82443LX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ID(PCI_DEVICE_ID_INTEL_82443BX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ID(PCI_DEVICE_ID_INTEL_82443GX_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ID(PCI_DEVICE_ID_INTEL_82810_MC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ID(PCI_DEVICE_ID_INTEL_82810_MC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ID(PCI_DEVICE_ID_INTEL_82810E_MC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ID(PCI_DEVICE_ID_INTEL_82815_MC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ID(PCI_DEVICE_ID_INTEL_82820_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ID(PCI_DEVICE_ID_INTEL_82830_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ID(PCI_DEVICE_ID_INTEL_82840_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ID(PCI_DEVICE_ID_INTEL_82845_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ID(PCI_DEVICE_ID_INTEL_82845G_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ID(PCI_DEVICE_ID_INTEL_82850_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ID(PCI_DEVICE_ID_INTEL_82854_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ID(PCI_DEVICE_ID_INTEL_82860_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ID(PCI_DEVICE_ID_INTEL_82865_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ID(PCI_DEVICE_ID_INTEL_82875_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ID(PCI_DEVICE_ID_INTEL_7505_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ID(PCI_DEVICE_ID_INTEL_7205_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ID(PCI_DEVICE_ID_INTEL_E7221_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ID(PCI_DEVICE_ID_INTEL_82915G_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ID(PCI_DEVICE_ID_INTEL_82945G_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ID(PCI_DEVICE_ID_INTEL_82G35_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ID(PCI_DEVICE_ID_INTEL_82965G_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ID(PCI_DEVICE_ID_INTEL_G33_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ID(PCI_DEVICE_ID_INTEL_Q35_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ID(PCI_DEVICE_ID_INTEL_Q33_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ID(PCI_DEVICE_ID_INTEL_GM45_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ID(PCI_DEVICE_ID_INTEL_Q45_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ID(PCI_DEVICE_ID_INTEL_G45_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ID(PCI_DEVICE_ID_INTEL_G41_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ID(PCI_DEVICE_ID_INTEL_B43_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct pci_driver agp_intel_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .name = "agpgart-intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .id_table = agp_intel_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .probe = agp_intel_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .remove = agp_intel_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .resume = agp_intel_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int __init agp_intel_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return pci_register_driver(&agp_intel_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static void __exit agp_intel_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pci_unregister_driver(&agp_intel_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) module_init(agp_intel_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) module_exit(agp_intel_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_AUTHOR("Dave Jones, Various @Intel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MODULE_LICENSE("GPL and additional rights");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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